Yusuke Matsunaga

发表

On acceleration methods of equivalence checking

松永裕介, Yusuke Matsunaga, 2002 .

Area Optimized Pipeline Scheduling with Initiation Interval and Allocation Constraints

松永裕介, Yusuke Matsunaga, 小玉翔, 2009 .

An Exact Approach for GPC-Based Compressor Tree Synthesis

Yusuke Matsunaga, Taeko Matsunaga, Shinji Kimura, 2013, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

Technology mapping technique for throughput enhancement of character projection equipment

Yusuke Matsunaga, Katsuya Okumura, Makoto Sugihara, 2006, SPIE Advanced Lithography.

Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits

Yusuke Matsunaga, Taiga Takata, Masayoshi Yoshimura, 2013, IPSJ Trans. Syst. LSI Des. Methodol..

Phase Optimization in Technology Mapping

Yusuke Matsunaga, 1995 .

A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only)

Yusuke Matsunaga, Taiga Takata, 2010, FPGA '10.

Multi-level logic optimization using binary decision diagrams

Masahiro Fujita, Yusuke Matsunaga, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Consideration and Evaluation on Dedicated Architecture for a Programable Controller

松永裕介, Yusuke Matsunaga, Daisuke Yamaguchi, 2003 .

Synthesis of parallel prefix adders considering switching activities

Yusuke Matsunaga, Taeko Matsunaga, Shinji Kimura, 2008, 2008 IEEE International Conference on Computer Design.

A Behavioral Synthesis Method with Special Functional Units

Yusuke Matsunaga, Tsuyoshi Sadakata, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Boolean resubstitution with permissible functions and binary decision diagrams

Masahiro Fujita, Yusuke Matsunaga, Hitomi Sato, 1991, DAC '90.

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs

Yusuke Matsunaga, Taiga Takata, 2009, GLSVLSI '09.

On a DAG - covering algorithm for technology mapping

Yusuke Matsunaga, 2004 .

Enhancing the performance of multi-cycle path analysis in an industrial setting

Hiroyuki Higuchi, Yusuke Matsunaga, 2004 .

Synthesis Algorithm for Parallel Index Generator

Yusuke Matsunaga, 2014, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

Yusuke Matsunaga, Taeko Matsunaga, Shinji Kimura, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

On Delay Minimum Mapping Algorithm for FPGAs Using Boolean Matching

松永裕介, Yusuke Matsunaga, 2002 .

A Simultaneous Module Selection, Scheduling, and Allocation Method Considering Operation Chaining with Multi-Functional Units

Yusuke Matsunaga, Tsuyoshi Sadakata, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits

Yusuke Matsunaga, Taiga Takata, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

Synthesis algorithm of parallel index generation units

Yusuke Matsunaga, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An Evaluation of Heuristic Fault Simulation Algorithms for Transient Faults in Sequential Circuits

Yusuke Matsunaga, Taiga Takata, Masayoshi Yoshimura, 2012 .

Variable ordering of binary decision diagrams for multi-level logic minimization

Yusuke Matsunaga, Masahiro Fujita, 1993 .

An Accelerating Technique for SAT-based ATPG

Yusuke Matsunaga, 2017, IPSJ Trans. Syst. LSI Des. Methodol..

Modeling of Latching Probability of Soft-Error-Induced Pulse

松永裕介, Yusuke Matsunaga, Masayoshi Yoshimura, 2010 .

Let's go to IEICE Workshops!: Technical Committee on VLSI Design Technologies (VLD)@@@VLSI設計技術研究会（VLD）

Yusuke Matsunaga, 2016 .

Special Section on Selected Papers from the 19th Workshop on Circuits and Systems in Karuizawa

Yusuke Matsunaga, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Test Pattern Compaction Method Using SAT-Based Fault Grouping

Yusuke Matsunaga, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

Masayoshi Tachibana, Yusuke Matsunaga, Tatsuo Ohtsuki, 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

TMR based Error Correction Method Considering Trade-offs between Soft Error Tolerance and Area

松永裕介, Yusuke Matsunaga, Masayoshi Yoshimura, 2010 .

Variable ordering algorithms for ordered binary decision diagrams and their evaluation

Masahiro Fujita, Yusuke Matsunaga, Hisanori Fujisawa, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Analysis of Soft Errors in Logic Circuits using Device Simulators

松永裕介, Yusuke Matsunaga, Masayoshi Yoshimura, 2010 .

An Approach To Generate Timing Constraints Considering Multiple Clocks

Yusuke Matsunaga, Taeko Matsunaga, Yutaka Tamiya, 1999 .

An efficient equivalence checker for combinational circuits

Yusuke Matsunaga, 1996, DAC '96.

Technology mapping technique for enhancing throughput of multi-column-cell systems

Yusuke Matsunaga, Makoto Sugihara, Kazuaki Murakami, 2007, SPIE Advanced Lithography.

Practical test architecture optimization for system-on-a-chip under floorplanning constraints

Yusuke Matsunaga, Makoto Sugihara, Kazuaki Murakami, 2004, IEEE Computer Society Annual Symposium on VLSI.

A fast state reduction algorithm for incompletely specified finite state machine

Hiroyuki Higuchi, Yusuke Matsunaga, 1996, DAC '96.

CP mask optimization for enhancing the throughput of MCC systems

Yusuke Matsunaga, Makoto Sugihara, Kazuaki Murakami, 2006, SPIE Photomask Technology.

Technology Mapping Technique for Increasing Throughput of Character Projection Lithography

Yusuke Matsunaga, Makoto Sugihara, Kazuaki Murakami, 2007, IEICE Trans. Electron..

Logic design system with evaluation-redesign mechanism

Yusuke Matsunaga, Fumihiro Maruyama, Yoriko Minoda, 1990 .

A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits

Yusuke Matsunaga, Taiga Takata, 2012, IPSJ Trans. Syst. LSI Des. Methodol..

On Asyncronous Circuits Design from A View Point of CAD techonologies

松永裕介, Yusuke Matsunaga, 2001 .

Binding Refinement for Multiplexer Reduction (IPSJ Transactions on System LSI Design Methodology Vol.2)

Yusuke Matsunaga, Sho Kodama, 2009 .

Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams

Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis

Yusuke Matsunaga, Tsuyoshi Sadakata, Y. Matsunaga, 2008, 2008 Asia and South Pacific Design Automation Conference.

Multi-Operand Adder Synthesis Targeting FPGAs

Yusuke Matsunaga, Taeko Matsunaga, Shinji Kimura, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Technique

Yusuke Matsunaga, 2016 .

Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs

Yusuke Matsunaga, Taiga Takata, 2009, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Evaluation on the Processor Archtecture for Programable Controller

松永裕介, Yusuke Matsunaga, Daisuke Yamaguchi, 2004 .

A New Algorithm for Boolean Matching Utilizing Structural Information

Yusuke Matsunaga, 1995, IEICE Trans. Inf. Syst..

Enhanced Unique Sensitization for Efficient Test Generation (Special Issue on Synthesis and Verification of Hardware Design)

Yusuke Matsunaga, Masahiro Fujita, 1993 .

An Evaluation of Approximate Methods for Soft Error Tolerance Evaluation of Sequential Circuits

松永裕介, Yusuke Matsunaga, Masayoshi Yoshimura, 2009 .

A Soft Error Tolerance Estimation Method for Sequential Circuits

Yusuke Matsunaga, Masayoshi Yoshimura, Yusuke Akamine, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

Multi-level logic minimization across latch boundaries

Masahiro Fujita, Yusuke Matsunaga, Takeo Kakuda, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

An Exact and Efficient Algorithms for Disjunctive Decomposition

Yusuke Matsunaga, 1998 .

An Evaluation Method for Soft Error Tolerance of Sequential Circuits with Markov Model

松永裕介, Yusuke Matsunaga, Masayoshi Yoshimura, 2009 .

Neutron-induced soft error rate estimation for SRAM using PHITS

Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

Implicit prime compatible generation for minimizing incompletely specified finite state machines

Hiroyuki Higuchi, Yusuke Matsunaga, 1995, ASP-DAC '95.

LP based cell selection with constraints of timing, area, and power consumption

Masahiro Fujita, Yusuke Matsunaga, Yutaka Tamiya, 1994, ICCAD '94.

The statistical longest path problem and its application to delay analysis of logical circuits

Yusuke Matsunaga, Masafumi Yamashita, Ei Ando, 2002, TAU '02.

Area minimization algorithm for parallel prefix adders under bitwise delay constraints

Yusuke Matsunaga, Taeko Matsunaga, Y. Matsunaga, 2007, GLSVLSI '07.

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment

Yusuke Matsunaga, Katsuya Okumura, Makoto Sugihara, 2006, IEICE Trans. Electron..

Evaluation of Calculation Method for Soft Error Propagation Rate in Combinational Circuit

松永裕介, Yusuke Matsunaga, 赤峰悠介, 2008 .

Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs

Yusuke Matsunaga, Taiga Takata, 2008, 2008 Asia and South Pacific Design Automation Conference.

A CP mask development methodology for MCC systems

Yusuke Matsunaga, Makoto Sugihara, Kazuaki Murakami, 2006, Photomask Japan.

Multi-Level Logic Minimization of Large Combinational Circuits by Partitioning

Masahiro Fujita, Yusuke Matsunaga, Kuang-Chien Chen, 1993 .

Binding Refinement for Multiplexer Reduction

Yusuke Matsunaga, Sho Kodama, Y. Matsunaga, 2009, IPSJ Trans. Syst. LSI Des. Methodol..

Multi-level logic minimization based on minimal support and its application to the minimization of look-up table type FPGAs

Masahiro Fujita, Yusuke Matsunaga, 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

On accelerating pattern matching for technology mapping

Yusuke Matsunaga, 1998, ICCAD.

Efficient FSM Traversal by Dynamic Removal of Flip - Flops

Hiroyuki Higuchi, Yusuke Matsunaga, 1998 .

On Computing the Transitive Closure of a State Transition Relation

Robert K. Brayton, Yusuke Matsunaga, Patrick C. McGeer, 1993, 30th ACM/IEEE Design Automation Conference.

On Functional Implication and Its Application to Equivalence Checking of Combinational Circuits

Yusuke Matsunaga, 1995 .

Framework for Parallel Prefix Adder Synthesis Considering Switching Activities

Yusuke Matsunaga, Taeko Matsunaga, Shinji Kimura, 2009, IPSJ Trans. Syst. LSI Des. Methodol..

Multi-operand adder synthesis on FPGAs using generalized parallel counters

Yusuke Matsunaga, Taeko Matsunaga, Shinji Kimura, 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

A resynthesis approach for network optimization

Masahiro Fujita, Yusuke Matsunaga, Saburo Muroga, 1991, 28th ACM/IEEE Design Automation Conference.

On variable ordering of binary decision diagrams for the application of multi-level logic synthesis

Masahiro Fujita, Yusuke Matsunaga, Taeko Kakuda, 1991, Proceedings of the European Conference on Design Automation..

A Character Size Optimization for Increasing the Throughput of Character Projection Lithography

Yusuke Matsunaga, Makoto Sugihara, Kazuaki Murakami, 2006 .

Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders

Yusuke Matsunaga, Taeko Matsunaga, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An Efficient SAT-Attack Algorithm Against Logic Encryption

Yusuke Matsunaga, Masayoshi Yoshimura, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Basic techniques for high-level synthesis

松永裕介, Yusuke Matsunaga, 2003 .

Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design

松永裕介, Yusuke Matsunaga, Masayoshi Yoshimura, 2009 .

A character size optimization technique for throughput enhancement of character projection lithography

Yusuke Matsunaga, Katsuya Okumura, Makoto Sugihara, 2006, 2006 IEEE International Symposium on Circuits and Systems.

An acceration of analyzing soft-error tolerance for sequential circuits

松永裕介, Yusuke Matsunaga, Masayoshi Yoshimura, 2010 .

Customizable Framework for Arithmetic Synthesis

松永裕介, Yusuke Matsunaga, Taeko Matsunaga, 2004 .

co-LODEX: A Cooperative Expert System for Logic design

Yusuke Matsunaga, Fumihiro Maruyama, Yoriko Minoda, 1988, FGCS.

TMR based Error Correction Method Considering Trade-off between Area and Soft-Error Tolerance

松永裕介, Yusuke Matsunaga, Masayoshi Yoshimura, 2010 .

Character Projection Mask Set Optimization for Enhancing Throughput of MCC Projection Systems

Yusuke Matsunaga, Makoto Sugihara, Kazuaki Murakami, 2008, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR technique

Yusuke Matsunaga, 2015, The 20th Asia and South Pacific Design Automation Conference.

Enhancing the performance of multi-cycle path analysis in an industrial setting

Hiroyuki Higuchi, Yusuke Matsunaga, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

On accelleration of SER analysis for sequential circuits using implicit enumeration

松永裕介, Yusuke Matsunaga, 赤峰悠介, 2009 .

An Iterative Improvement Method for State Minimization of Incompletely Specified Finite State Machines (Special Issue on Synthesis and Verification of Hardware Design)

Hiroyuki Higuchi, Yusuke Matsunaga, 1997 .

Special Section on VLSI Design and CAD Algorithms

Yusuke Matsunaga, 2007, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Power-aware Post-processing under depth constraint for LUT-based FPGA Technology Mapping

松永裕介, Yusuke Matsunaga, Taiga Takata, 2009 .

Multi-level logic optimization

Masahiro Fujita, Yusuke Matsunaga, Maciej Ciesielski, 2001 .

An Efficient Algorithm Finding Simple Disjoint Decompositions Using BDDs

Yusuke Matsunaga, 2002, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

MINT-An Exact Algorithm for Finding Minimum Test Set (Special Section on VLSI Design and CAD Algorithms)

Yusuke Matsunaga, 1993 .