J.Y.C. Sun

State-of-the-art RF/analog foundry technology

J.C.H. Lin, T. H. Yeh, C. Y. Lee, 2002, Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting.

A 0.18 /spl mu/m CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications

K.Y. Lee, J.Y.C. Sun, K.L. Young, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Scaling variance, invariance and prediction of design rule: from 0.25-/spl mu/m to 0.10-/spl mu/m nodes in the era of foundry manufacturing

J. K. Wang, J.Y.C. Sun, Sunnys Hsieh, 2001, 2001 6th International Workshop on Statistical Methodology (Cat. No.01TH8550).

Foundry technology for the next decade

J.Y.C. Sun, Shang-Yi Chiang, M. Liu, 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).