S. Mukhopadhyay

Process variation in embedded memories: failure analysis and variation aware architecture

B.C. Paul, K. Roy, A. Agarwal, 2005, IEEE Journal of Solid-State Circuits.

Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory

Dongkyu Park, K. Roy, Keejong Kim, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

Independent gate skewed logic in double-gate SOI technology

K. Roy, H. Mahmoodi, S. Mukhopadhyay, 2005, 2005 IEEE International SOI Conference Proceedings.

Modeling and estimation of failure probability due to parameter variations in nano-scale SRAMs for yield enhancement

K. Roy, H. Mahmoodi-Meimand, S. Mukhopadhyay, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

High performance and low power domino logic using independent gate control in double-gate SOI MOSFETs

K. Roy, H. Mahmoodi, S. Mukhopadhyay, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design

Ching-Te Chuang, P. Oldiges, K. Roy, 2006, IEEE Electron Device Letters.

Accurate modeling of transistor stacks to effectively reduce total standby leakage in nano-scale CMOS circuits

K. Roy, S. Mukhopadhyay, 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

Device-Optimization Technique for Robust and Low-Power FinFET SRAM Design in NanoScale Era

K. Roy, A. Bansal, S. Mukhopadhyay, 2007, IEEE Transactions on Electron Devices.

Leakage in nanometer scale CMOS circuits

C. Neau, K. Roy, H. Mahmoodi-Meimand, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).