O. Takahashi

A streaming processing unit for a CELL processor

B. Flachs, S. Asano, S.H. Dhong, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

A 1.0 GHz single-issue 64 b powerPC integer processor

O. Takahashi, K. Nowka, I. Vo, 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

The circuits and physical design of the synergistic processor element of a CELL processor

B. Flachs, S.H. Dhong, O. Takahashi, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro

S.H. Dhong, O. Takahashi, R.H. Dennard, 2000, IEEE Journal of Solid-State Circuits.

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

O. Takahashi, D. Wendel, S.R. Cottier, 2008, IEEE Journal of Solid-State Circuits.

A 1 GHz single-issue 64 b PowerPC processor

B. Flachs, O. Takahashi, K. Nowka, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

S.H. Dhong, O. Takahashi, A. Kawasumi, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

The Power Conscious Synergistic Processor Element of a Cell Processor

B. Flachs, S.H. Dhong, O. Takahashi, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

1 GHz fully pipelined 3.7 ns address access time 8 k/spl times/1024 embedded DRAM macro

O. Takahashi, M. Wordeman, R. Dennard, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

S.H. Dhong, O. Takahashi, H. Murakami, 2006, IEEE Journal of Solid-State Circuits.