S.L.J. Gierkink

A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator

S.L.J. Gierkink, 2008, IEEE Journal of Solid-State Circuits.

A robust 43 GHz VCO in standard CMOS for OC-768 SONET applications

B. Nauta, V. Boccuzzi, R.C. Frye, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

A robust 43-GHz VCO in CMOS for OC-768 SONET applications

B. Nauta, V. Boccuzzi, R.C. Frye, 2004, IEEE Journal of Solid-State Circuits.

Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump

S.L.J. Gierkink, S. Gierkink, 2008, IEEE Journal of Solid-State Circuits.

A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver

V. Boccuzzi, R.C. Frye, S.L.J. Gierkink, 2005, IEEE Journal of Solid-State Circuits.

A low–phase–noise 5GHz quadrature CMOS VCO using common–mode inductive coupling

V. Boccuzzi, R.C. Frye, S. Levantino, 2002, Proceedings of the 28th European Solid-State Circuits Conference.