D. Storaska

A 2.9ns random access cycle embedded DRAM with a destructive-read

T. Kirihata, Chomg-Lii Hwang, M. Wordernan, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

G. Daniel, D. Hanson, M. Wordeman, 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

Advanced controlling scheme for a DRAM voltage generator system

D. Storaska, O. Weinfurtner, L. Hsu, 2000, IEEE Journal of Solid-State Circuits.

A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture

G. Daniel, M. Wordeman, T. Kirihata, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

10+ gb/s 90-nm CMOS serial link demo in CBGA package

S. Reynolds, S. Gowda, B. Floyd, 2005, IEEE Journal of Solid-State Circuits.