Ajit Pal

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Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence

Sumanta Pyne, Ajit Pal, 2013, VDAT.

Low Power Sensor Node for a Wireless Sensor Network

Ajit Pal, Akepati Sravan, Sujan Kundu, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

An algorithm for finding a non-trivial lower bound for channel routing

Sudebkumar Prasant Pal, Ajit Pal, Rajat K. Pal, 1997, Proceedings Tenth International Conference on VLSI Design.

NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic

Sudebkumar Prasant Pal, Ajit Pal, Rajat K. Pal, 1993, The Sixth International Conference on VLSI Design.

A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks

Puneet Jain, Indranil Sengupta, Ajit Pal, 2008, 2008 16th IEEE International Conference on Networks.

A load balanced approach of multicast routing and wavelength assignment in WDM networks

Ajit Pal, Tanmay De, Subhendu Barat, 2015, Int. J. Commun. Networks Distributed Syst..

Supply Voltage Scaling for Low Power

Ajit Pal, A. Pal, 2015 .

Splitting minimization: a novel approach for multicasting in WDM mesh networks

Ajit Pal, Tanmay De, Subhendu Barat, 2014 .

Battery-Aware Systems

Ajit Pal, A. Pal, 2015 .

Leakage Power Minimization

Ajit Pal, 2015 .

A Novel Technology Mapping Technique for BDD-Based Circuits Using LEAP Cells

Bhargab B. Bhattacharya, Ajit Pal, Gopal Paul, 2010, 2010 International Symposium on Electronic System Design.

Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework

Pallab Dasgupta, Ajit Pal, Rajdeep Mukherjee, 2012, 2012 International Symposium on Electronic System Design (ISED).

Assisted-Leach (A-Leach) Energy Efficient Routing Protocol for Wireless Sensor Networks

Sunkara Vinodh Kumar, Ajit Pal, A. Pal, 2013 .

Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning

Indranil Sengupta, Ajit Pal, Tanmay De, 2008, ICDCN.

Studies in logic synthesis, testing, and security issues of digital circuits based on binary decision diagrams

Bhargab B. Bhattacharya, Ajit Pal, Gopal Paul, 2011 .

Energy-aware logic synthesis and technology mapping for MUX-based FPGAs

Ajit Pal, Maitrali Marik, 2004, 17th International Conference on VLSI Design. Proceedings..

Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent Swarm

Subrata Nandi, Ajit Pal, Suman Paul, 2010, ICDCN.

Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks

Ajit Pal, Umesh Patel, 2004, IWDC.

Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent

Pallab Dasgupta, Ajit Pal, Srobona Mitra, 2010, Design Automation Conference.

Synthesis and Testing for Low Power

Ajit Pal, 2009 .

An efficient interchangeable switch-box router: a generalized study

Ajit Pal, Rajat Kumar Pal, 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design

Ajit Pal, Mallikarjuna Rao Nimmagadda, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Optimal assignment of high threshold voltage for synthesizing dual threshold CMOS circuits

Nikhil Tripathi, Ajit Pal, Debasis Samanta, 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

Dynamic location management with variable size location areas

Ajit Pal, D. S. Khati, 2001, Proceedings 2001 International Conference on Computer Networks and Mobile Computing.

Data Communication and Computer Networks

Ajit Pal, A. Pal, 2014 .

Yield Aware Approach for Low Power Synthesis

Ajit Pal, Arundhati Jana, 2006, 2006 International Conference on Electrical and Computer Engineering.

A Microprocessor-Based Temperature Monitoring and Control System

Ajit Pal, A. K. Sanyal, 1985 .

Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic

Bhargab B. Bhattacharya, Ajit Pal, S. N. Pradhan, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Formal Verification of Hardware / Software Power Management Strategies

Subhankar Mukherjee, Pallab Dasgupta, Ajit Pal, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Switched Capacitance Minimization

Ajit Pal, 2015 .

Information management in large scale networks

Niloy Ganguly, Subrata Nandi, Ajit Pal, 2011 .

Loop unrolling with fine grained power gating for runtime leakage power reduction

Sumanta Pyne, Ajit Pal, 2014, 18th International Symposium on VLSI Design and Test.

Characterization of Unate Cascade Realizability Using Parameters

Ajit Pal, A. K. Choudhury, S. Bandyopadhyay, 1975, IEEE Transactions on Computers.

Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence

Sumanta Pyne, Ajit Pal, 2015, J. Low Power Electron..

A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation

Sudip Roy, Ajit Pal, A. Pal, 2010, Journal of Low Power Electronics.

Impact of Leakage Power Reduction Techniques on Parametric Yield - Low-Power Design of Digital Integrated Circuits under Process Parameter Variations

Sudip Roy, Ajit Pal, 2013 .

An algorithm for finding a non-trivial lower bound for channel routing1

Sudebkumar Prasant Pal, Ajit Pal, Rajat K. Pal, 1998, Integr..

Resolving horizontal constraints and minimizing net wire length for multi-layer channel routing

Amitava Datta, Rajat Kumar Pal, Ajit Pal, 1993, Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation.

A GRAPH ALGORITHM FOR FINDING THE MINIMUM TEST SET OF A BDD-BASED CIRCUIT

Bhargab B. Bhattacharya, Ajit Pal, Gopal Paul, 2007 .

Automated synthesis of combinational circuits by cascade networks of multiplexers

Ajit Pal, R. K. Gorai, 1990 .

An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing

Ajit Pal, Rajat K. Pal, 1992, The Fifth International Conference on VLSI Design.

Cellular realization of TSC checkers for error detecting codes

Ajit Pal, 1990, IEEE TENCON'90: 1990 IEEE Region 10 Conference on Computer and Communication Systems. Conference Proceedings.

State assignment of finite state machines for optimal implementation using MUXs

Ajit Pal, R. K. Gora, 1991, TENCON '91. Region 10 International Conference on EC3-Energy, Computer, Communication and Control Systems.

Formal Verification of Architectural Power Intent

Pallab Dasgupta, Ajit Pal, Aritra Hazra, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Synthesis of dual-V/sub T/ dynamic CMOS circuits

Ajit Pal, Debasis Samanta, D. Samanta, 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

A power-aware wireless sensor network based bridge monitoring system

Sudip Roy, Ajit Pal, Sujan Kundu, 2008, 2008 16th IEEE International Conference on Networks.

Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture

Pallab Dasgupta, Ajit Pal, Rajdeep Mukherjee, 2012, ACITY.

A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture pdf

Pallab Dasgupta, Ajit Pal, Rajdeep Mukherjee, 2013, VLSIC 2013.

Synthesis of high performance low power PTL circuits

Ajit Pal, Debasis Samanta, M. C. Dharmadeep, 2003, ASP-DAC '03.

Realization of power aware software prefetching as a multi-objective optimization problem

Sumanta Pyne, Ajit Pal, Krishanu Ray, 2011, 2011 2nd International Conference on Computer and Communication Technology (ICCCT-2011).

Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating

Sumanta Pyne, Ajit Pal, A. Pal, 2015, J. Low Power Electron..

Traffic grooming in WDM mesh networks using dynamic path selection strategy

Ajit Pal, Tanmay De, Sukanta Bhattacharya, 2010, 2010 Seventh International Conference on Wireless and Optical Communications Networks - (WOCN).

Location management and paging using mobility pattern

M. Pandey, Ajit Pal, 2003, 9th Asia-Pacific Conference on Communications (IEEE Cat. No.03EX732).

Proceedings of the 7th international conference on Distributed Computing

Ajay D. Kshemkalyani, Arobinda Gupta, Ajit Pal, 2005 .

Low-Power VLSI Circuits and Systems

Ajit Pal, A. Pal, 2014 .

Synthesis & Testing for Low Power

Santanu Chattopadhyay, Ajit Pal, 2009, 2009 22nd International Conference on VLSI Design.

Synthesis of high performance low power dynamic CMOS circuits

Ajit Pal, Debasis Samanta, Nishant Sinha, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Low-Power Software Approaches

Ajit Pal, 2015 .

An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis

Pallab Dasgupta, Ajit Pal, Rajdeep Mukherjee, 2013, J. Low Power Electron..

A new lower bound for channel routing

Rajat Kumar Pal, Ajit Pal, Sundar Pal, 1993, Proceedings of TENCON '93. IEEE Region 10 International Conference on Computers, Communications and Automation.

Optimal dual-V/sub T/ assignment for low-voltage energy-constrained CMOS circuits

Ajit Pal, Debasis Samanta, D. Samanta, 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques

Sumanta Pyne, Ajit Pal, 2012, J. Low Power Electron..

Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?

Sudip Roy, Ajit Pal, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

MOS Combinational Circuits

Ajit Pal, A. Pal, 2015 .

A general graph theoretic framework for multi-layer channel routing

Sudebkumar Prasant Pal, Ajit Pal, Rajat K. Pal, 1995, Proceedings of the 8th International Conference on VLSI Design.

Extending light-trail into elastic optical networks for dynamic traffic grooming

Ajit Pal, Tanmay De, Prasanta Majumdar, 2016, Opt. Switch. Netw..

Distributed dynamic grooming routing and wavelength assignment in WDM optical mesh networks

Puneet Jain, Ajit Pal, Tanmay De, 2010, Photonic Network Communications.

YIELDAWARE APPROACH FORLOW POWER SYNTHESIS

Ajit Pal, Arundhati Jana, 2006 .

Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning

Indranil Sengupta, Ajit Pal, Tanmay De, 2010, Photonic Network Communications.

On finding the minimum test set of a BDD-based circuit

Bhargab B. Bhattacharya, Ajit Pal, Gopal Paul, 2006, GLSVLSI '06.

POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent

Ansuman Banerjee, Subhankar Mukherjee, Pallab Dasgupta, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Computing area and wire length efficient routes for channels

Sudebkumar Prasant Pal, Ajit Pal, Rajat K. Pal, 1995, Proceedings of the 8th International Conference on VLSI Design.

Synthesis of low power high performance dual-V/sub T/ PTL circuits

Ajit Pal, Debasis Samanta, 2004, 17th International Conference on VLSI Design. Proceedings..

Synthesis of two-level dynamic CMOS circuits

Ajit Pal, A. Mukherjee, 1999, Proceedings. IEEE Computer Society Workshop on VLSI '99. System Design: Towards System-on-a-Chip Paradigm.

Logic design using digital summation threshold-logic gates

Ajit Pal, A. Pal, 1983 .