Sung-Geun Kim

A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO

Dae Hyun Kwon, Woo-Young Choi, Jinsoo Rhim, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 0.4-V, 500-MHz, ultra-low-power phase-locked loop for near-threshold voltage operation

Dae Hyun Kwon, Woo-Young Choi, Joung-Wook Moon, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

A 32-Gb/s PAM-4 Quarter-Rate Clock and Data Recovery Circuit With an Input Slew-Rate Tolerant Selective Transition Detector

Woo-Young Choi, Sung-Geun Kim, Dae-Hyun Kwon, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 990-$\mu\hbox{W}$ 1.6-GHz PLL Based on a Novel Supply-Regulated Active-Loop-Filter VCO

Woo-Young Choi, Bhum-Cheol Lee, Seung-Woo Lee, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Integration of dual channel timing formatter system for high speed memory test equipment

Seong-Ook Jung, Sungho Kang, Woo-Young Choi, 2012, 2012 International SoC Design Conference (ISOCC).

A low-voltage PLL with a current mismatch compensated charge pump

Woo-Young Choi, Jinsoo Rhim, Min-Hyeong Kim, 2015, 2015 International SoC Design Conference (ISOCC).

A 5–8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization

Dae Hyun Kwon, Woo-Young Choi, Tongsung Kim, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).