Haridimos T. Vergos

发表

A Unifying Approach for Weighted and Diminished-1 Modulo $2^n+1$ Addition

Haridimos T. Vergos, Costas Efstathiou, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

New architectures for modulo 2N - 1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

On the Yield of VLSI Processors with on-chip CPU Cache

Haridimos T. Vergos, Dimitris Nikolos, 1996, EDCC.

Reconfigurable CPU Cache Memory Design : Fault Tolerance and Performance Evaluation

Haridimos T. Vergos, Dimitris Nikolos, Petros Mitsiadis, 1997 .

Extending the viability of power signature — Based IP watermarking in the SoC era

Haridimos T. Vergos, George Blanas, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Efficient modulo 2n+1 adder architectures

Haridimos T. Vergos, Costas Efstathiou, C. Efstathiou, 2009, Integr..

A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks

Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, 1999, EDCC.

A class of easily path delay fault testable circuits

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Haridimos T. Vergos, 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).

Efficient BIST schemes for RNS datapaths

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Reverse converters for RNSs with diminished-one encoded channels

Haridimos T. Vergos, Evangelos Vassalos, Dimitris Bakalis, 2013, Eurocon 2013.

High speed parallel-prefix modulo 2/sup n/+1 adders for diminished-one operands

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components

Haridimos T. Vergos, Dimitris Bakalis, 2008, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools.

Efficient modulo 2n + 1 multi-operand adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Bakalis, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Deterministic BIST for RNS Adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, IEEE Trans. Computers.

On Implementing Efficient Modulo 2n + 1 Arithmetic Components

Haridimos T. Vergos, Dimitris Bakalis, 2010, J. Circuits Syst. Comput..

Area-time efficient end-around inverted carry adders

Haridimos T. Vergos, 2012, Integr..

Easily verified IP watermarking

Haridimos T. Vergos, Anastasios N. Bikos, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

KoVer : a sophisticated residue arithmetic core generator

Haridimos T. Vergos, Nikolaos Kostaras, H. T. Vergos, 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

Efficient modulo 2/sup n/+1 tree multipliers for diminished-1 operands

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

On accumulator-based bit-serial test response compaction schemes

Haridimos T. Vergos, Dimitris Nikolos, Dimitris Bakalis, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Diminished-One Modulo 2n+1 Adder Design

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2002, IEEE Trans. Computers.

On the Design of Modulo 2n±1 Subtractors and Adders/Subtractors

Haridimos T. Vergos, Evangelos Vassalos, Dimitris Bakalis, 2011, Circuits Syst. Signal Process..

SUT-RNS Residue-to-Binary Converters Design

Haridimos T. Vergos, Evangelos Vassalos, Dimitris Bakalis, 2012, 2012 15th Euromicro Conference on Digital System Design.

RNS multiplication/sum-of-squares units

Haridimos T. Vergos, D. Adamidis, 2007, IET Comput. Digit. Tech..

Efficient modulo 2n±1 squarers

Haridimos T. Vergos, Dimitris Bakalis, A. Spyrou, 2011, Integr..

Performance recovery in direct-mapped faulty caches via the use of a very small fully associative spare cache

Haridimos T. Vergos, D. Nokolos, 1995, Proceedings of 1995 IEEE International Computer Performance and Dependability Symposium.

Path delay fault testing of ICs with embedded intellectual property blocks

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Haridimos T. Vergos, 1999, DATE '99.

Modulo 2n±1 Adder Design Using Select-Prefix Blocks

Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou, 2003, IEEE Trans. Computers.

An efficient BIST scheme for high-speed adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Area-Efficient Multi-moduli Squarers for RNS

Haridimos T. Vergos, Dimitris Bakalis, 2010, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools.

On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation

Emmanouil Kalligeros, Haridimos T. Vergos, George Alexiou, 2002, J. Syst. Archit..

Reprints Available Directly from the Publisher Photocopying Permitted by License Only (c) 2001 Opa (overseas Publishers Association) N.v. Low Power Built-in Self-test Schemes for Array and Booth Multipliers*

Haridimos T. Vergos, George Alexiou, Dimitris Nikolos, 2022 .

SUT-RNS Forward and Reverse Converters

Haridimos T. Vergos, Evangelos Vassalos, Dimitris Bakalis, 2010, ISVLSI.

Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion

Haridimos T. Vergos, Evangelos Vassalos, Dimitris Bakalis, 2011, 2011 14th Euromicro Conference on Digital System Design.

Design and Analysis of On-Chip CPU Pipelined Caches

Haridimos T. Vergos, Dimitris Nikolos, C. Ninos, 1999, VLSI.

On Modulo 2^n+1 Adder Design

Giorgos Dimitrakopoulos, Haridimos T. Vergos, G. Dimitrakopoulos, 2012, IEEE Transactions on Computers.

Lookahead Architectures for Hamming Distance and Fixed-Threshold Hamming Weight Comparators

Haridimos T. Vergos, Dimitris Bakalis, A. Anastasiou, 2015, Circuits Syst. Signal Process..

On path delay fault testing of multiplexer-based shifters

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Michael Nicolaidis, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches

Haridimos T. Vergos, Dimitris Nikolos, Spyros Voulgaris, 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Area-time efficient multi-modulus adders and their applications

Haridimos T. Vergos, Dimitris Bakalis, 2012, Microprocess. Microsystems.

Low power dissipation in BIST schemes for modified Booth multipliers

Haridimos T. Vergos, George Alexiou, Dimitris Nikolos, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Fast parallel-prefix modulo 2/sup n/+1 adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2004, IEEE Transactions on Computers.

SUT-RNS Forward and Reverse Converters

Haridimos T. Vergos, Evangelos Vassalos, Dimitris Bakalis, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

High-Speed Parallel-Prefix Modulo 2n-1 Adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2000, IEEE Trans. Computers.

RNS assisted image filtering and edge detection

Haridimos T. Vergos, Evangelos Vassalos, Dimitris Bakalis, 2013, 2013 18th International Conference on Digital Signal Processing (DSP).

Design of efficient modulo 2n+1 multipliers

Haridimos T. Vergos, Costas Efstathiou, 2007, IET Comput. Digit. Tech..

Fast modulo 2n+1 multi-operand adders and residue generators

Haridimos T. Vergos, Costas Efstathiou, Dimitris Bakalis, 2010, Integr..

Efficient diminished-1 modulo 2/sup n/ + 1 multipliers

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2005, IEEE Transactions on Computers.

Path delay fault testing of Benes multistage interconnection networks

Haridimos T. Vergos, Dimitris Nikolos, M. Bellos, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

An Efficient BIST Scheme for Non-Restoring Array Dividers

Haridimos T. Vergos, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Diminished-1 Modulo 2n + 1 Squarer Design

Haridimos T. Vergos, Costas Efstathiou, C. Efstathiou, 2005, DSD.

A family of parallel-prefix modulo 2/sup n/-1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

Fast parallel-prefix Ling-carry adders in QCA nanotechnology

Alexios Thanos, Haridimos T. Vergos, 2013, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS).

On the Design of Efficient Modular Adders

Haridimos T. Vergos, Costas Efstathiou, 2005, J. Circuits Syst. Comput..

Low power BIST for Wallace tree-based multipliers

Emmanouil Kalligeros, Haridimos T. Vergos, George Alexiou, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

A Family of Area-Time Efficient Modulo 2n+1 Adders

Haridimos T. Vergos, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

On the Yield of VLSI Processors with On-Chip CPU Cache

Haridimos T. Vergos, Dimitris Nikolos, 1999, IEEE Trans. Computers.

An Efficient BIST Scheme for Non-Restoring Array Dividers

Haridimos T. Vergos, 2007 .

Efficient fault tolerant cache memory design

Haridimos T. Vergos, Dimitris Nikolos, D. Nikolos, 1995, Microprocess. Microprogramming.

Diminished-1 modulo 2n+1 squarer design

Haridimos T. Vergos, Costas Efstathiou, 2005 .

Handling zero in diminished-one modulo 2 n + 1 adders

Haridimos T. Vergos, Dimitris Nikolos, Constantinos Efstathiou, 2003 .

Easily testable carry-save multipliers with respect to path delay faults

Michael Nicolaidis, Haridimos T. Vergos, Dimitris Nikolos, 1999 .