Costas Efstathiou

发表

A Unifying Approach for Weighted and Diminished-1 Modulo $2^n+1$ Addition

Haridimos T. Vergos, Costas Efstathiou, 2008, IEEE Transactions on Circuits and Systems II: Express Briefs.

An Efficient TSC 1-out-of-3 Code Checker

Constantin Halatsis, Antonis M. Paschalis, Costas Efstathiou, 1990, IEEE Trans. Computers.

Detecting untestable hardware Trojan with non-intrusive concurrent on line testing

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Ling adders in CMOS standard cell technologies

Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos, 2002, 9th International Conference on Electronics, Circuits and Systems.

On the design of modulo 2/sup n//spl plusmn/1 adders

Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

SecurID Authenticator: On the Hardware Implementation Efficiency

Costas Efstathiou, Nicolas Sklavos, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

New architectures for modulo 2N - 1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

A concurrent BIST scheme for read only memories

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

On the Design of Configurable Modulo 2n±1 Residue Generators

Kiamal Z. Pekmestzi, Costas Efstathiou, Nikolaos Moschopoulos, 2012, 2012 15th Euromicro Conference on Digital System Design.

Test Set Embedding into Low-Power BIST Sequences Using Maximum Bipartite Matching

Ioannis Voyiatzis, Costas Efstathiou, Nikolaos S. Papaspyrou, 2012, 2012 16th Panhellenic Conference on Informatics.

Efficient modulo 2n+1 adder architectures

Haridimos T. Vergos, Costas Efstathiou, C. Efstathiou, 2009, Integr..

A systematic methodology for designing area-time efficient parallel-prefix modulo 2/sup n/ - 1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

On the design of modulo 2n±1 residue generators

Kiamal Z. Pekmestzi, Costas Efstathiou, Nikolaos Moschopoulos, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Efficient BIST schemes for RNS datapaths

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Stealth Assessment of Hardware Trojans in simple Processors

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2014, Panhellenic Conference on Informatics.

High speed parallel-prefix modulo 2/sup n/+1 adders for diminished-one operands

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

Efficient modulo 2n + 1 multi-operand adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Bakalis, 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

Input Vector Monitoring Concurrent BIST Architecture Using SRAM Cells

Ioannis Voyiatzis, Costas Efstathiou, C. Efstathiou, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An efficient architecture for accumulator-based test generation of SIC pairs

Costas Efstathiou, I. Voyiatzis, 2008, DTIS 2008.

Deterministic BIST for RNS Adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, IEEE Trans. Computers.

Transparent testing for intra-word memory faults

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2013, 2013 8th IEEE Design and Test Symposium.

On the use of hard faults to generate test sets

Ioannis Voyiatzis, Costas Efstathiou, C. Efstathiou, 2015, Panhellenic Conference on Informatics.

Modulo 2n+1 addition and multiplication for redundant operands

Kiamal Z. Pekmestzi, Costas Efstathiou, Kostas Tsoumanis, 2014, 2014 9th International Design and Test Symposium (IDT).

Efficient modulo 2/sup n/+1 tree multipliers for diminished-1 operands

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

Diminished-One Modulo 2n+1 Adder Design

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2002, IEEE Trans. Computers.

Low Cost Boolean Function generation

Ioannis Voyiatzis, Costas Efstathiou, 2016, PCI.

An efficient architecture for accumulator-based test generation of SIC pairs

Ioannis Voyiatzis, Costas Efstathiou, 2008, 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era.

A Virtual Signalling Protocol for Transparently Embedding Advanced Traffic Control and Resource Management Functionality in ATM Core Networks

George Kormentzas, Costas Efstathiou, Kimon P. Kontovasilis, 2003, MMNS.

SIC pair generation in near-optimal time with carry-look ahead adders

Ioannis Voyiatzis, Costas Efstathiou, 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Efficient modulo 2n+1 multiplication for the idea block cipher

Kiamal Z. Pekmestzi, Costas Efstathiou, Nikolaos Moschopoulos, 2013, GLSVLSI '13.

Area-time efficient modulo 2/sup n/-1 adder design

Costas Efstathiou, Dimitris Nikolos, John Kalamatianos, 1994 .

Modulo 2n ± 1 Fused Add-Multiply Units

Kiamal Z. Pekmestzi, Ioannis Voyiatzis, Costas Efstathiou, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Concurrent detection of soft errors based on current monitoring

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Costas Efstathiou, 2001, Proceedings Seventh International On-Line Testing Workshop.

Testable Designs of Multiple Precharged Domino Circuits

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Costas Efstathiou, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On Embedding Test Sets into Hardware Generated Sequences

Ioannis Voyiatzis, Dimitris J. Kavvadias, Costas Efstathiou, 2010, 2010 14th Panhellenic Conference on Informatics.

A Low-Cost Optimal Time SIC Pair Generator

Costas Efstathiou, I. Voyiatzis, H. Antonopoulou, 2010 .

A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture

Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, 2011, 2011 Sixteenth IEEE European Test Symposium.

An efficient BIST scheme for high-speed adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Test set embedding into hardware generated sequences using an embedding algorithm

Cleo Sgouropoulou, Ioannis Voyiatzis, Dimitris J. Kavvadias, 2015, 2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkers

Yiorgos Tsiatouhas, Costas Efstathiou, Dimitris Nikolos, 2003 .

Fused modulo 2n + 1 add-multiply unit for weighted operands

Kiamal Z. Pekmestzi, Costas Efstathiou, Kostas Tsoumanis, 2016, 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).

Modular design of totally self-checking checkers for 1-out-of-n codes

Constantin Halatsis, Costas Efstathiou, 1984, Fehlertolerierende Rechensysteme.

Low Power and High Speed Static CMOS Digital Magnitude Comparators

Yiorgos Tsiatouhas, Costas Efstathiou, K. Dimolikas, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Embedding test vectors in accumulator - based TPG using progressive search

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Fused modulo 2n − 1 add-multiply unit

Kiamal Z. Pekmestzi, Costas Efstathiou, Kostas Tsoumanis, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

New High-Speed Multioutput Carry Look-Ahead Adders

Yiorgos Tsiatouhas, Costas Efstathiou, Zaher Owda, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Fast parallel-prefix modulo 2/sup n/+1 adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2004, IEEE Transactions on Computers.

On the Design of Modulo 2^n+1 Multipliers

Kiamal Z. Pekmestzi, Costas Efstathiou, Nicholas Axelos, 2011, 2011 14th Euromicro Conference on Digital System Design.

High-Speed Parallel-Prefix Modulo 2n-1 Adders

Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos, 2000, IEEE Trans. Computers.

A Family of Parallel-Pre.x Modulo 2n - 1 Adders.

Giorgos Dimitrakopoulos, Costas Efstathiou, Haridimos T. Vergos, 2003 .

Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding

Kiamal Z. Pekmestzi, Costas Efstathiou, Nikolaos Moschopoulos, 2014, Integr..

Design of efficient modulo 2n+1 multipliers

Haridimos T. Vergos, Costas Efstathiou, 2007, IET Comput. Digit. Tech..

Fast modulo 2n+1 multi-operand adders and residue generators

Haridimos T. Vergos, Costas Efstathiou, Dimitris Bakalis, 2010, Integr..

Efficient diminished-1 modulo 2/sup n/ + 1 multipliers

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2005, IEEE Transactions on Computers.

Arithmetic module-based built-in self test architecture for two-pattern testing

Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, 2012, IET Comput. Digit. Tech..

On the generation of binary functions with low-overhead

Ioannis Voyiatzis, Costas Efstathiou, 2017, 2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Accumulator-based generation for serial TPG

Ioannis Voyiatzis, Costas Efstathiou, 2015, Panhellenic Conference on Informatics.

Diminished-1 Modulo 2n + 1 Squarer Design

Haridimos T. Vergos, Costas Efstathiou, C. Efstathiou, 2005, DSD.

A family of parallel-prefix modulo 2/sup n/-1 adders

Giorgos Dimitrakopoulos, Haridimos T. Vergos, Costas Efstathiou, 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

Test set embedding into accumulator-generated sequences targeting hard-to-detect faults

Cleo Sgouropoulou, Maria K. Michael, Ioannis Voyiatzis, 2013, 2013 8th IEEE Design and Test Symposium.

Low overhead output response compaction in RAS architectures

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Efficient modulo 2N+1 subtractors for weighted operands

Costas Efstathiou, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Accumulator-based self-adjusting output data compression for embedded word-organized DRAMs

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Symmetric transparent online BIST for arrays of word-organized RAMs

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Programmable logic for single-output functions

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Implementation of HSSec: a high-speed cryptographic co-processor

Constantinos E. Goutis, Athanasios Kakarountas, Costas Efstathiou, 2007, 2007 IEEE Conference on Emerging Technologies and Factory Automation (EFTA 2007).

An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator

Kiamal Z. Pekmestzi, Costas Efstathiou, Sotirios Xydis, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A low-cost input vector monitoring concurrent BIST scheme

Cleo Sgouropoulou, Ioannis Voyiatzis, Costas Efstathiou, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

On the design of modulo 2n + 1 dot product and generalized multiply-add units

Kiamal Z. Pekmestzi, Ioannis Voyiatzis, Costas Efstathiou, 2013, Comput. Electr. Eng..

Software-based SIC pair Generation

Ioannis Voyiatzis, Costas Efstathiou, Kiriakos Patriarcheas, 2016, PCI.

An effective two-pattern test generator for Arithmetic BIST

Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou, 2013, Comput. Electr. Eng..

Exploiting cryptographic architectures over hardware vs. software implementations: advantages and trade-offs

Costas Efstathiou, Nicolas Sklavos, K. Touliou, 2006 .

Efficient majority logic magnitude comparator design

Paris Kitsos, Costas Efstathiou, C. Efstathiou, 2021, Microprocess. Microsystems.

Diminished-1 modulo 2n+1 squarer design

Haridimos T. Vergos, Costas Efstathiou, 2005 .