Naofumi Nakamura

Fabrication of 35nm via-hole patterns for interconnect test chips with EUV lithography

Kazuo Tawarayama, Shunko Magoshi, Hajime Aoyama, 2010, Advanced Lithography.

Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects

Kazuo Tawarayama, Hajime Aoyama, Yuusuke Tanaka, 2010, Advanced Lithography.