Hori Yohei

发表

Preliminary experimental platform for FlexPower FPGA evaluation

Katashita Toshihiro, Hioki Masakazu, Hori Yohei, 2016 .

On Machine Learning Attack Tolerance for PUF-based Device Authentication System

Katashita Toshihiro, Hori Yohei, Ikeda Makoto, 2019 .

Physical-level detection approach against hardware Trojans inside semiconductor chips (I)

Nagata Makoto, Matsumoto Tsutomu, Hori Yohei, 2019 .

FPGA Implementation of a key generation circuit using PUF and Fuzzy Extractor on SASEBO-G3

Katashita Toshihiro, Hori Yohei, 2015 .

Implementation and Experimental Evaluation of Physically Unclonable Functions in 180nm CMOS Process

Fujino Takeshi, Katashita Toshihiro, Hori Yohei, 2019 .

Performance Evaluation of Physical Unclonable FUnctions on Kintex-7 FPGA

Katashita Toshihiro, Hori Yohei, Kobara Kazukuni, 2013 .

Design and Implementation of Self Run-time Partial Reconfiguration System

Hori Yohei, Toda Kenji, Yokoyama Hiroyuki, 2007 .

Quantitative Performance Evaluation of Arbiter PUFs on FPGAs

Katashita Toshihiro, Hori Yohei, Yoshida Takahiro, 2010 .

Content protection system based on partial reconfiguration of FPGA

Hori Yohei, Toda Kenji, Yokoyama Hiroyuki, 2006 .

Development and Evaluation of Cryptographic Hardware Generated by Behavior-level Synthesis

Hori Yohei, Imai Hideki, Itoh Mai, 2009 .

Development of Standard Evaluation Environment for Side-channel Attacks and Countermeasures

Katashita Toshihiro, Hori Yohei, Satoh Akashi, 2009 .

A Comparative Study of CPA and MIA on Side-channel Attack Standard Evaluation Boards

Hori Yohei, Imai Hideki, Taguchi Asuka, 2010 .

Development of Side-channel Attack Standard Evaluation BOard and Tool

Katashita Toshihiro, Hori Yohei, Toda Kenji, 2008 .

Magnetic Field Measurement for Side-channel Analysis Environment

Katashita Toshihiro, Hori Yohei, Satoh Akashi, 2010 .

A Study on Dependence between Performance Metrics of PUFs and the Number of Response Bits using PUF Numerical Model

Fujino Takeshi, Hori Yohei, Shiozaki Mitsuru, 2019 .

Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems

Hori Yohei, Toda Kenji, Satoh Akashi, 2008, 2008 International Conference on Field Programmable Logic and Applications.

A Rapid Verification Environment for Statistical Evaluation of PUF Circuits

Katashita Toshihiro, Hori Yohei, Onda Yasunori, 2015 .

Versatile Media Processor for Super High Definition (VMP/SHD) -- The scalable architecture of parallel overlay frame engine

Katashita Toshihiro, Hori Yohei, Toda Kenji, 2007 .

Performance Evaluation for PUF-based Authentication Systems with Shift Post-processing

Katashita Toshihiro, Hori Yohei, Satoh Akashi, 2010 .

Versatile media processor utilizing multiple overlay frames -- capable of multi-display and contents-security

Katashita Toshihiro, Hori Yohei, Toda Kenji, 2006 .

PL-PUF Implementation by Improvement of Capturing Timing Control Circuit

Hori Yohei, Ogasahara Yasuhiro, Koike Hanpei, 2018 .