M. Fujita

A 6,000-gate CMOS gate array

H. Yoshimura, T. Itoh, M. Takechi, 1982, 1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A CMOS 12K gate array with flexible 10Kb memory

T. Itoh, M. Takechi, M. Fujita, 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

FAM 17.1: A CMOS I2K-Gate Array with Flexible 10Kb Memory

Kunihiko Ikuzaki, M. Fujita, Makoto Takechi, 1983 .

Building block approach and variable size memory for CMOS VLSIs

M. Fujita, K. Ikuzaki, A. Masaki, 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Design of CMOS masterslice logic LSI

Kunihiko Ikuzaki, M. Fujita, Makoto Takechi, 1983 .

Compact Size and High Output Power Er-Doped Fiber Amplifier Modules Pumped with 1.48 Microns MQW LDs,

M. Fujita, H. Okuno, H. Takenaka, 1992 .

Evolution of dynamic gaits for a robot

M. Fujita, T. Yamamoto, J. Yokono, 2000, 2000 Digest of Technical Papers. International Conference on Consumer Electronics. Nineteenth in the Series (Cat. No.00CH37102).

A dual polarization patch rectenna for high power application

M. Fujita, M. Ishii, N. Ogihara, 1996, IEEE Antennas and Propagation Society International Symposium. 1996 Digest.

Debugging a communications chip

M. Fujita, 1996, IEEE Spectrum.

A 250 Mb/s 1 Gb double data rate SDRAM with a bi-directional delay and an inter-bank shared redundancy scheme

Y. Takai, M. Fujita, H. Ohkubo, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 30 ns 256 Mb DRAM with multi-divided array structure

T. Matano, N. Kasai, M. Fujita, 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.