J. Jopling

Using An Engineering Analysis Process To Identify Pragmatic Applications For Solid Expandable Tubular Technology

D. Mason, G. Cales, M. Holland, 2005 .

High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors

J. Jopling, J. Neirynck, H. Deshpande, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Erratic fluctuations of sram cache vmin at the 90nm process technology node

J. Jopling, M. Jones, M. Agostinelli, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

J. Jopling, C. Prasad, T. Ghani, 2009, 2009 IEEE International Reliability Physics Symposium.

Tunnel current measurements on P/N junction diodes and implications for future device design

J. Jopling, O. Dokumaci, P. Ronsheim, 2003, IEEE International Electron Devices Meeting 2003.

Dielectric breakdown in a 45 nm high-k/metal gate process technology

J. Jopling, M. Agostinelli, C. Prasad, 2008, 2008 IEEE International Reliability Physics Symposium.