Roger Loo

发表

Mid-IR heterogeneous silicon photonics

Chen Hu, Richard M. Osgood, Li Shen, 2013, Photonics West - Optoelectronic Materials and Devices.

Material Studies on Si:C Epitaxial Films Grown by CVD

Wilfried Vandervorst, Roger Loo, Sathishkumar Dhayalan, 2014 .

GeSn Technology: Impact of Sn on Ge CMOS Applications

Roger Loo, Yosuke Shimura, Matty Caymax, 2011 .

Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other Stress Techniques

Geert Hellings, Eddy Simoen, Liesbeth Witters, 2011 .

Use of a Purged FOUP to Improve H-Terminated Silicon Surface Stability Prior to Epitaxial Growth

Stefan De Gendt, Roger Loo, Andriy Hikavyy, 2014 .

Ultimate nano-electronics

Jerome Mitard, Rita Rooyackers, Anne Vandooren, 2015 .

Non silicon CMOS devices: research curiosity or key to future products?

Geert Hellings, Cor Claeys, Jerome Mitard, 2014 .

Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET

Naoto Horiguchi, Geert Hellings, Liesbeth Witters, 2018, Microelectron. Reliab..

In-line and nondestructive analysis of selectively grown epitaxial Si1-xGex and Si/ Si1-xGex layers by spectroscopic ellipsometery and comparison with other established techniques

Roger Loo, Matty Caymax, Stephanie Kremer, 2001, Microelectronic and MEMS Technologies.

Selective Epitaxy of Si/SiGe to Improve pMOS Devices by Recessed Source/Drain and/or Buried SiGe Channels

Akira Inoue, Rita Rooyackers, Denis Shamiryan, 2006 .

Group IV Epi processing, evolution in CMOS from 90 to 10nm node

Robert Langer, Roger Loo, Wei Wang, 2014 .

Stress Techniques and Mobility Enhancement in FinFET Architectures

Naoto Horiguchi, Geert Hellings, Anabela Veloso, 2013 .

Assessment of Ge1-xSnx Alloys for Strained Ge CMOS Devices

Roger Loo, Yosuke Shimura, Tsuyoshi Nishimura, 2010 .

Laser annealed in-situ P-doped Ge for on-chip laser source applications (Conference Presentation)

Yosuke Shimura, Roger Loo, Joris Van Campenhout, 2016, Photonics Europe.

Layout Scaling of {Si}_{1-x}{Ge}_{x} {-Channel} pFETs

Jerome Mitard, Liesbeth Witters, C. Ortolland, 2011 .

Quantifying self-heating effects with scaling in globally strained Si MOSFETs

Sarah H. Olsen, Roger Loo, Yang Yang, 2007 .

Germanium-on-silicon mid-infrared waveguides and Mach-Zehnder interferometers

Gunther Roelkens, Muhammad Muneeb, Roger Loo, 2013, 2013 IEEE Photonics Conference.

Selective Epitaxial Growth of InP in STI Trenches on Off-Axis Si (001) Substrates

Gang Wang, Marc Heyns, Roger Loo, 2010 .

High Absorption Contrast Quantum Confined Stark Effect in Ultra-Thin Ge/SiGe Quantum Well Stacks Grown on Si

Jeroen De Coster, Roger Loo, Joris Van Campenhout, 2020, IEEE Journal of Quantum Electronics.

Silicon-Based Photonic Integration Beyond the Telecommunication Wavelength Range

Gunther Roelkens, Utsav Dave, Alban Gassenq, 2014, IEEE Journal of Selected Topics in Quantum Electronics.

Silicon-based heterogeneous photonic integrated circuits for the mid-infrared

Joris Van Campenhout, Gunther Roelkens, Alban Gassenq, 2013 .

Porous silicon as an intermediate layer for thin-film solar cell

Johan Nijs, Roger Loo, Jef Poortmans, 2001 .

Ge1−xSnx stressors for strained-Ge CMOS

Roger Loo, Akira Sakai, Yosuke Shimura, 2011 .

Identification of Deep Levels Associated with Extended and Point Defects in GeSn Epitaxial Layers using DLTS

Eddy Simoen, Marc Heyns, Roger Loo, 2013 .

Ge-on-Si and Ge-on-SOI thermo-optic phase shifters for the mid-infrared.

Gunther Roelkens, Muhammad Muneeb, Roger Loo, 2014, Optics express.

Reduced Self-Heating by Strained Silicon Substrate Engineering

Enrico Sangiorgi, Claudio Fiegna, Sarah H. Olsen, 2007 .

Fabrication and Analysis of a Heterojunction Line Tunnel FET

Rita Rooyackers, Anne Vandooren, Aaron Thean, 2014 .

Undoped and in-situ B doped GeSn epitaxial growth on Ge by atmospheric pressure-chemical vapor deposition

Wilfried Vandervorst, Marc Heyns, Roger Loo, 2011 .

High-Performance Si0.45Ge0.55 Implant-Free Quantum Well pFET With Enhanced Mobility by Low-Temperature Process and Transverse Strain Relaxation

Naoto Horiguchi, Geert Hellings, Jerome Mitard, 2014, IEEE Transactions on Electron Devices.

High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO2Gate Dielectric

Jerome Mitard, Jacopo Franco, Luigi Pantisano, 2011 .

Low-temperature pre-epitaxy surface cleaning of Si and SiGe

Roger Loo, Andriy Hikavyy, Sandeep Mehta, 2015 .

Strain and Compositional Analysis of (Si)Ge Fin Structures Using High Resolution X‐Ray Diffraction

Naoto Horiguchi, Liesbeth Witters, Wilfried Vandervorst, 2017 .

Solid-State Electronics: Editorial

Roger Loo, Roger Loo, Steven J. Koester, 2013 .

The Influence of the Epitaxial Growth Process Parameters on Layer Characteristics and Device Performance in Si-passivated Ge pMOSFETs

Jerome Mitard, Wilfried Vandervorst, Roger Loo, 2009 .

Development of a new type of SiGe thin strain relaxed buffer based on the incorporation of a carbon-containing layer

Wilfried Vandervorst, Roger Loo, Romain Delhougne, 2004 .

Crystalline Properties and Strain Relaxation Mechanism of CVD Grown GeSn

Wilfried Vandervorst, Marc Heyns, Roger Loo, 2013 .

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth

Rita Rooyackers, Nadine Collaert, Malgorzata Jurczak, 2008 .

The implant-free quantum well field-effect transistor: Harnessing the power of heterostructures☆

Geert Hellings, Jerome Mitard, Niamh Waldron, 2012 .

SiGe SEG Growth for Buried Channels p-MOS Devices

Liesbeth Witters, Roger Loo, Andriy Hikavyy, 2009 .

Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel

Geert Hellings, Jerome Mitard, Liesbeth Witters, 2010, 2010 International Electron Devices Meeting.

High performance Si/SiGe pMOSFETs fabricated in a standard CMOS process technology

Nadine Collaert, Roger Loo, K. De Meyer, 2003 .

(Invited) Selective Etch of Si and SiGe for Gate All-Around Device Architecture

Naoto Horiguchi, Liesbeth Witters, Aaron Thean, 2015 .

Stress Techniques in Advanced Transistor Architectures: Bulk FinFETs and Implant-Free Quantum Well Transistors

Naoto Horiguchi, Geert Hellings, Jerome Mitard, 2012 .

Invited) Status and Trends in Ge CMOS Technology

Geert Hellings, Cor Claeys, Jerome Mitard, 2013 .

The vertical heterojunction MOSFET

Nadine Collaert, Roger Loo, Kristin De Meyer, 1998 .

Implant free SiGe quantum well: from device concept to high-performing pFETs

Naoto Horiguchi, Geert Hellings, Jerome Mitard, 2013 .

Thin epitaxial si films as a passivation method for Ge(100) : Influence of deposition temperature on ge surface segregation and the high-k/Ge interface quality

Paul Zimmerman, Ben Kaczer, Wilfried Vandervorst, 2006 .