Marius Bonaciu

Using abstract CPU subsystem simulation model for high level HW/SW architecture exploration

Ahmed Amine Jerraya, Iuliana Bacivarov, Wassim Youssef, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

Software Performance Estimation in MPSoC Design

Ahmed Amine Jerraya, Wander O. Cesário, Flávio Rech Wagner, 2007, 2007 Asia and South Pacific Design Automation Conference.

Software for Multi Processor System on Chip: Moving an MPEG4 Decoder from Generic RISC Platforms to CELL

Paul Amblard, Marius Bonaciu, Ludovic Demontes, 2008, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping.

High-level architecture exploration for MPEG4 encoder with custom parameters

Xi Chen, Ahmed Amine Jerraya, Wander O. Cesário, 2006, Asia and South Pacific Conference on Design Automation, 2006..

An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory

Amer Baghdadi, Ahmed Amine Jerraya, Soo-Ik Chae, 2004, Proceedings. 41st Design Automation Conference, 2004..

Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application

Ahmed Amine Jerraya, Lorenzo Pieralisi, Iuliana Bacivarov, 2006, Proceedings of the Design Automation & Test in Europe Conference.

An efficient architecture for the implementation of message passing programming model on massive multiprocessor

Amer Baghdadi, Ahmed Amine Jerraya, Wander O. Cesário, 2004, Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004..