Binsu J Kailath

Analysis and design of low power nonlinear PFD architectures for a fast locking PLL

K. K. Abdul Majeed, Binsu J Kailath, 2016, 2016 IEEE Students’ Technology Symposium (TechSym).

A Novel Method to Implement STDP Learning Rule in Verilog

Binsu J Kailath, Amrutha Manoharan, Gadamsetty Muralidhar, 2020, 2020 IEEE Region 10 Symposium (TENSYMP).

Design of optimized MAC unit using integrated vedic multiplier

Nandita Bhaskhar, Binsu J Kailath, Monisha Yuvaraj, 2017, 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS).

Accelerating Occupancy Grid Map Computation with GPU for Real-Time Obstacle Detection

Dinesh Kumar, Rajesh Kumar, Sudha Natarajan, 2016, 2016 22nd Annual International Conference on Advanced Computing and Communication (ADCOM).

Switched capacitor circuit simulator for noise analysis using adjoint network approach

Binsu J Kailath, Vani Mrudula Magapati, 2017, 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS).

A Silicon Neuron-based Bio-Front-End for Ultra Low Power Bio-Monitoring at the Edge

Tara Julia Hamilton, Gaetano Gargiulo, Binsu J Kailath, 2020, 2020 IEEE Symposium Series on Computational Intelligence (SSCI).

The simplest and efficient form of Spiking Neuron

Binsu J Kailath, Muralidhar Gadamsetty, 2019, 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

High speed Power efficient Vedic arithmetic modules on Zedboard-Zynq-7000 FPGA

Binsu J Kailath, S Sujitha, 2021, Int. J. Circuit Theory Appl..

Graph based Circuit Simulator for Switched Capacitor Circuits

G. Dinesh, Binsu J Kailath, 2021 .