Ch. Kernstock

Interface traps density-of-states as a vital component for hot-carrier degradation modeling

Tibor Grasser, Oliver Triebl, Hajdin Ceric, 2010, Microelectronics and reliability.

Predictive physical simulation of III/V quantum-well MISFETs for logic applications

Markus Karner, Zoran Stanojevic, Hans Kosina, 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

Cell Designer - a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells

K. Steiner, Markus Karner, Zoran Stanojevic, 2018, 2018 48th European Solid-State Device Research Conference (ESSDERC).

Hot-carrier degradation modeling using full-band Monte-Carlo simulations

E. Seebacher, T. Grasser, H. Ceric, 2010, 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits.

Interface states charges as a vital component for hc degradation modeling.

E. Seebacher, Tibor Grasser, Christoph Jungemann, 2010 .