Spyros Tragoudas

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Low Power Artificial Neural Network Architecture pdf

Krishna Prasad Gnawali, Seyed Nima Mozaffari, Spyros Tragoudas, 2019, ArXiv.

Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture

Spyros Tragoudas, Edward Flanigan, Rajsekhar Adapa, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

A novel coarse-grain reconfigurable data-path for accelerating DSP kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, FPGA '04.

Improved approximations for the minimum-cut ratio and the flux

Spyros Tragoudas, S. Tragoudas, 1996, Mathematical systems theory.

On-chip embedding mechanisms for large sets of vectors for delay test

Spyros Tragoudas, Vijay Nagarandal, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Occurrence probability analysis of a path at the architectural level

Spyros Tragoudas, Dheepakkumaran Jayaraman, S. Tragoudas, 2011, 2011 12th International Symposium on Quality Electronic Design.

The Problem of Partitioning with Duplications and its Applications

Spyros Tragoudas, James Haralambides, 1994, Int. J. Artif. Intell. Tools.

Fast Approximation Algorithms for Multicommodity Flow Problems

Fillia Makedon, Spyros Tragoudas, Éva Tardos, 1995, J. Comput. Syst. Sci..

A novel approach to minimizing reconfiguration cost for LUT-based FPGAs

Haibo Wang, Spyros Tragoudas, Krishna Prasad Raghuraman, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

Scalable identification of threshold logic functions

Spyros Tragoudas, Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, 2010, GLSVLSI '10.

On minimizing hardware overhead for pseudoexhaustive circuit testability

Fillia Makedon, Spyros Tragoudas, Dimitrios Kagaris, 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

Scalable codeword generation for coupled buses

Spyros Tragoudas, Kedar Karmarkar, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Methods for on-chip embedding of path delay test vectors

Spyros Tragoudas, Dimitrios Kagaris, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

A critical path selection method for delay testing

Spyros Tragoudas, S. Padmanaban, 2004 .

An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic

Spyros Tragoudas, Michael N. Skoufis, 2012, IEEE Transactions on Computers.

A Data Capturing Method for Buses on Chip

Spyros Tragoudas, Themistoklis Haniotakis, Kedar Karmarkar, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Scalable Fault Coverage Estimation of Sequential Circuits without Fault Injection

Spyros Tragoudas, Pavan Kumar Javvaji, Ganesh Kondapuram, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Pseudoexhaustive BIST for sequential circuits

Dinesh Bhatia, Spyros Tragoudas, Dimitrios Kagaris, 1993, Proceedings of 1993 IEEE International Conference on Computer Design ICCD'93.

Testing for path delay faults using test points

Spyros Tragoudas, N. Denny, S. Tragoudas, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Detection of Low Power Trojans in Standard Cell Designs using Built-in Current Sensors

Spyros Tragoudas, Basim Shanyour, 2018, 2018 IEEE International Test Conference (ITC).

A new built-in TPG method for circuits with random patternresistant faults

Spyros Tragoudas, Dimitris Nikolos, Dimitris Bakalis, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Retiming-Based Partial Scan

Spyros Tragoudas, Dimitrios Kagaris, 1996, IEEE Trans. Computers.

Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures

Spyros Tragoudas, Edward Flanigan, Arkan Abdulrahman, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Diagnosis with transition faults on embedded segments

Spyros Tragoudas, Theodoros Toulas, 2017, 2017 IEEE 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS).

A novel parallel adaptation of an implicit path delay grading method

Spyros Tragoudas, Joseph Lenox, 2014, GLSVLSI '14.

A new method to identify threshold logic functions

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Glitch Control with Dynamic Receiver Threshold Adjustment

Haibo Wang, Spyros Tragoudas, Themistoklis Haniotakis, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A Novel Test Generation Methodology for Adaptive Diagnosis

Spyros Tragoudas, Edward Flanigan, R. Adapa, 2008, ISQED 2008.

A Probabilistic Approach to Diagnose SETs in Sequential Circuits

Spyros Tragoudas, Sreenivas Gangadhar, 2013, J. Electron. Test..

Identification of delay defects on embedded paths using one current sensor

Spyros Tragoudas, Themistoklis Haniotakis, Wisam Aljubouri, 2016, 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).

An Aging Resilient Neural Network Architecture

Krishna Prasad Gnawali, Seyed Nima Mozaffari, Spyros Tragoudas, 2018, 2018 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

ATPG for path delay faults without path enumeration

Spyros Tragoudas, Maria K. Michael, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Functional-based ATPG for path delay faults

Spyros Tragoudas, Maria K. Michael, 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).

InTeRail: using existing and extra interconnects to test core-based SOCs

Spyros Tragoudas, Dimitrios Kagaris, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

A High-Performance Bus Architecture for Strongly Coupled Interconnects

Spyros Tragoudas, Themistoklis Haniotakis, M. N. Skoufis, 2008, ISQED 2008.

Identification of Critical Executable Paths at the Architectural Level

Spyros Tragoudas, Chunrong Song, S. Tragoudas, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design and evaluation of a security scheme for sensor networks

Spyros Tragoudas, Themistoklis Haniotakis, Khadija Stewart, 2005, Sixth international symposium on quality electronic design (isqed'05).

An efficient algorithm for finding a path subject to two additive constraints

Spyros Tragoudas, Marwan Krunz, Turgay Korkmaz, 2000, SIGMETRICS '00.

Improved Threshold Logic Synthesis Using Implicant-Implicit Algorithms

Spyros Tragoudas, Ashok Kumar Palaniswamy, S. Tragoudas, 2014, ACM J. Emerg. Technol. Comput. Syst..

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, FPL.

Power-aware test pattern generation for improved concurrency at the core level

Spyros Tragoudas, Arkan Abdulrahman, S. Tragoudas, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays

Spyros Tragoudas, Pavan Kumar Javvaji, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Operations on Multiple Transition Faults without Enumeration

Spyros Tragoudas, Theodoros Toulas, 2016 .

METS: A multiple event transient simulator

Spyros Tragoudas, Adam Watkins, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A Probabilistic Approach to Diagnose SETs

Spyros Tragoudas, Sreenivas Gangadhar, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

A comparative study of five language independent programming environments

Panayiotis E. Pintelas, Spyros Tragoudas, 1991, J. Syst. Softw..

On-line detection of random voltage perturbations in buses with multiple-threshold receivers

Spyros Tragoudas, Michael N. Skoufis, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

A method to determine the sensitization probability of a non-robustly testable path

Spyros Tragoudas, Dheepakkumaran Jayaraman, 2013, International Symposium on Quality Electronic Design (ISQED).

Non-enumerative path delay fault diagnosis [logic testing]

Spyros Tragoudas, S. Padmanaban, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

A novel probabilistic SET propagation method

Spyros Tragoudas, Sreenivas Gangadhar, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Automatic Test Pattern Generation

Spyros Tragoudas, 2006 .

Quickest paths: parallelization and dynamization

Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis, 1995, Proceedings of the Twenty-Eighth Annual Hawaii International Conference on System Sciences.

Circuit partitioning into small sets: a tool to support testing with further applications

Fillia Makedon, Spyros Tragoudas, R. Farrell, 1991, Proceedings of the European Conference on Design Automation..

Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model

Spyros Tragoudas, Edward Flanigan, Dheepakkumaran Jayaraman, 2008, 2008 IEEE International Test Conference.

Maximizing the Number of Threshold Logic Functions Using Resistive Memory

Seyed Nima Mozaffari, Spyros Tragoudas, S. Tragoudas, 2018, IEEE Transactions on Nanotechnology.

Approximating the minimum net expansion: Near optimal solutions to circuit partitioning problems

Fillia Makedon, Spyros Tragoudas, 1990, WG.

A Scalable Method for Identifying DNA Substrings Using Functions

Spyros Tragoudas, Pragyan P. Mohanty, 2011, BICoB.

Test-set partitioning for multi-weighted random LFSRs

Spyros Tragoudas, Amitava Majumdar, Dimitrios Kagaris, 2000, Integr..

Sub-faults identification for collapsing in diagnosis

Spyros Tragoudas, Rajsekhar Adapa, Maria K. Michael, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Color counting and its application to path delay fault coverage

Spyros Tragoudas, Jayant Deodhar, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Interconnect testing for networks on chips

Spyros Tragoudas, Khadija Stewart, S. Tragoudas, 2006, 24th IEEE VLSI Test Symposium.

ATPD: an automatic test pattern generator for path delay faults

Spyros Tragoudas, Dimitrios Karayiannis, 1996, Proceedings International Test Conference 1996. Test and Design Validity.

A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations

Spyros Tragoudas, Manoj Kumar Goparaju, S. Tragoudas, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds

Spyros Tragoudas, Dimitrios Kagaris, 2003, J. Electron. Test..

Maximum independent sets on transitive graphs and their applications in testing and CAD

Spyros Tragoudas, Dimitrios Kagaris, 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

Exact Path Delay Fault Coverage with Fundamental Zero-Suppressed BDD Operations

Spyros Tragoudas, Maria K. Michael, S. Padmanaban, 2007 .

On-line testing field programmable analog array circuits

Spyros Tragoudas, Haibo Wang, S. Kulkarni, 2004 .

High-Quality Transition Fault ATPG for Small Delay Defects

Spyros Tragoudas, Mahilchi Milir Vaseekar Kumar, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

On-line testing field programmable analog array circuits

Haibo Wang, Spyros Tragoudas, Suchitra Kulkarni, 2004, 2004 International Conferce on Test.

Delay Analysis for an N-Input Current Mode Threshold Logic Gate

Spyros Tragoudas, Themistoklis Haniotakis, Chandra Babu Dara, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Searching a Pseudo 3-Sided Solid Orthoconvex Grid

Spyros Tragoudas, Antonios Symvonis, 1993, Int. J. Found. Comput. Sci..

An implicit path-delay fault diagnosis methodology

Spyros Tragoudas, Saravanan Padmanaban, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Clustering Network Modules with Different Implementations for Delay Minimization

Spyros Tragoudas, Dimitrios Karayiannis, S. Tragoudas, 1998, VLSI Design.

An efficient algorithm for finding a path subject to two additive constraints

Spyros Tragoudas, Marwan Krunz, Turgay Korkmaz, 2002, Comput. Commun..

Efficient deterministic test generation for BIST schemes with LFSR reseeding

Spyros Tragoudas, Maria K. Michael, Stelios Neophytou, 2006, 12th IEEE International On-Line Testing Symposium (IOLTS'06).

A fault tolerant threshold logic gate design

Spyros Tragoudas, Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, 2009 .

Compressive image sensor technique with sparse measurement matrix

Haibo Wang, Spyros Tragoudas, Stefan Leitner, 2016, 2016 29th IEEE International System-on-Chip Conference (SOCC).

A nonenumerative ATPG for functionally sensitizable path delay faults

Spyros Tragoudas, Dimitrios Karayiannis, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

An improved method for identifying linear dependencies in path delay faults

Spyros Tragoudas, Edward Flanigan, Themistoklis Haniotakis, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Mathematical model for routability analysis of FPGAs

Dinesh Bhatia, Spyros Tragoudas, Amit Chowdhary, 1994, Proceedings of 4th Great Lakes Symposium on VLSI.

A Novel Test Generation Methodology for Adaptive Diagnosis

Spyros Tragoudas, Edward Flanigan, Rajsekhar Adapa, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Circuit partitioning into small sets

Fillia Makedon, Spyros Tragoudas, Robert Farell, 1992, Microprocess. Microsystems.

On-chip deterministic counter-based TPG with low heat dissipation

Spyros Tragoudas, Dimitris Nikolos, Xrysovalantis Kavousianos, 1999, 1999 Southwest Symposium on Mixed-Signal Design (Cat. No.99EX286).

Prioritization of Paths for Diagnosis

Spyros Tragoudas, Rajsekhar Adapa, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

Performance validation through implicit removal of infeasible paths of the behavioral description

Spyros Tragoudas, Dheepakkumaran Jayaraman, 2013, International Symposium on Quality Electronic Design (ISQED).

A class of good characteristic polynomials for LFSR test pattern generators

Spyros Tragoudas, Dimitrios Kagaris, 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

A high performance data-path to accelerate DSP kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

An Adaptive Path Delay Fault Diagnosis Methodology

Spyros Tragoudas, Saravanan Padmanaban, 2004 .

Rewiring for watermarking digital circuits

Spyros Tragoudas, M. Moiz Khan, S. Tragoudas, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates

Spyros Tragoudas, Manoj Kumar Goparaju, Sandeep Dechu, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

An adaptive path delay fault diagnosis methodology [logic IC testing]

Spyros Tragoudas, Saravanan Padmanaban, 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

Transient pulse propagation using the Weibull distribution function

Spyros Tragoudas, Adam Watkins, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Low power and high speed current-mode memristor-based TLGs

Spyros Tragoudas, Themistoklis Haniotakis, Chandra Babu Dara, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Fast march tests for defects in resistive memory

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2015, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15).

Enhanced Identification of Strong Robustly Testable Paths

Spyros Tragoudas, Edward Flanigan, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Evaluation of collapsing methods for fault diagnosis

Spyros Tragoudas, Rajsekhar Adapa, Maria K. Michael, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Avoiding linear dependencies in LFSR test pattern generators

Spyros Tragoudas, Dimitrios Kagaris, 1995, J. Electron. Test..

Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets

Spyros Tragoudas, Dimitrios Kagaris, 1993, IEEE Trans. Very Large Scale Integr. Syst..

Routing with energy considerations in mobile ad-hoc networks

Spyros Tragoudas, S. Dimitrova, 2000, 2000 IEEE Wireless Communications and Networking Conference. Conference Record (Cat. No.00TH8540).

Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model

Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms

Spyros Tragoudas, Dimitrios Kagaris, Dimitrios Karayiannis, 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements

Spyros Tragoudas, Ahish Mysore Somashekar, 2013, International Symposium on Quality Electronic Design (ISQED).

Graph Theory and Algorithms

Spyros Tragoudas, Dimitrios Kagaris, S. Tragoudas, 2007, Wiley Encyclopedia of Computer Science and Engineering.

InTeRail: a test architecture for core-based SOCs

Spyros Tragoudas, Dimitrios Kagaris, Sherin Kuriakose, 2006, IEEE Transactions on Computers.

Nonenumerative path delay fault coverage estimation with optimal algorithms

Spyros Tragoudas, Dimitrios Kagaris, Dimitrios Karayiannis, 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

Maximum weighted independent sets on transitive graphs and applications1

Spyros Tragoudas, Dimitrios Kagaris, S. Tragoudas, 1999, Integr..

Improved diagnosis using enhanced fault dominance

Spyros Tragoudas, Rajsekhar Adapa, Maria K. Michael, 2011, Integr..

A BIST approach for counterfeit circuit detection based on NBTI degradation

Spyros Tragoudas, Puneet Ramesh Savanur, Phaninder Alladi, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Broadside ATPG for Low Power Trojans Detection using Built-in Current Sensors

Spyros Tragoudas, Basim Shanyour, 2020, 2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS).

Exact path delay fault coverage with fundamental ZBDD operations

Spyros Tragoudas, Maria K. Michael, Saravanan Padmanaban, 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Functional ATPG for delay faults

Spyros Tragoudas, Maria K. Michael, S. Tragoudas, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Error Correction Encoding for Tightly Coupled On-Chip Buses

Spyros Tragoudas, Kedar Karmarkar, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Implicit Critical PDF Test Generation with Maximal Test Efficiency

Spyros Tragoudas, Maria K. Michael, Kyriakos Christou, 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

On Channel Routing Problems with Interchangeable Terminals

Spyros Tragoudas, 1994 .

A Novel Data-Path for Accelerating DSP Kernels

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, SAMOS.

Quality transition fault tests suitable for small delay defects

Spyros Tragoudas, Mahilchi Milir Vaseekar Kumar, 2005, 2005 International Conference on Computer Design.

Identification of Delay Measurable PDFs Using Linear Dependency Relationships

Spyros Tragoudas, Edward Flanigan, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design Techniques for Direct Digital Synthesis Circuits with Improved Frequency Accuracy Over Wide Frequency Ranges

Haibo Wang, Spyros Tragoudas, Stefan Leitner, 2017, J. Circuits Syst. Comput..

Aging-aware critical paths for process related validation in the presence of NBTI

Spyros Tragoudas, Phaninder Alladi, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

A method for hardware metering

Spyros Tragoudas, M. Moiz Khan, S. Tragoudas, 2005 .

LFSR/SR pseudoexhaustive TPG in fewer test cycles

Spyros Tragoudas, Dimitrios Kagaris, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission

Spyros Tragoudas, Themistoklis Haniotakis, Khadija Stewart, 2012, Ad Hoc Networks.

Implicit and exact path delay fault grading in sequential circuits

Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi, 2005, Design, Automation and Test in Europe.

Generation of hazard identification functions

Spyros Tragoudas, Maria K. Michael, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Accelerating Diagnosis via Dominance Relations between Sets of Faults

Spyros Tragoudas, Rajsekhar Adapa, Maria K. Michael, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

BOARD LEVEL PARTITIONING FOR IMPROVED PARTIAL SCAN

Spyros Tragoudas, 1995 .

Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement

Spyros Tragoudas, Maria K. Michael, Stelios Neophytou, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Interchanging terminals for improved channel routing

Spyros Tragoudas, I. G. Tollis, 1990, IEEE International Symposium on Circuits and Systems.

Min-Cut Partitioning on Underlying Tree and Graph Structures

Spyros Tragoudas, S. Tragoudas, 1996, IEEE Trans. Computers.

Approximation algorithms for VLSI partition problems

Fillia Makedon, Spyros Tragoudas, Tom Leighton, 1990, IEEE International Symposium on Circuits and Systems.

Deterministic test pattern reproduction by a counter

Spyros Tragoudas, Amitava Majumdar, Dimitrios Kagaris, 1996, Proceedings ED&TC European Design and Test Conference.

Test set identification for improved delay defect coverage in the presence of statistical delays

Spyros Tragoudas, Pavan Kumar Javvaji, Basim Shanyour, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

Compact ATPG for concurrent SOC testing

Spyros Tragoudas, Arkan Abdulrahman, 2004, Fifth International Workshop on Microprocessor Test and Verification (MTV'04).

Pseudo-exhaustive built-in TPG for sequential circuits

Dinesh Bhatia, Spyros Tragoudas, Dimitrios Kagaris, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A high-performance data path for synthesizing DSP kernels

Spyros Tragoudas, Michalis D. Galanis, George Theodoridis, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accurate path delay fault coverage is feasible

Spyros Tragoudas, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

ATPG tools for Delay Faults at the Functional Level *

Spyros Tragoudas, Maria K. Michael, S. Tragoudas, 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

A High-Performance Bus Architecture for Strongly Coupled Interconnects

Spyros Tragoudas, Themistoklis Haniotakis, Kedar Karmarkar, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Techniques for improved diagnosis

Spyros Tragoudas, R. Adapa, 2008 .

Quickest Paths: Parallelizat ion and Dynamizat ion

Spyros Tragoudas, Grammati E. Pantziou, Dimitrios Kagaris, 1995 .

Minmax-cut graph partitioning problems

Spyros Tragoudas, S. Tragoudas, 1993, [1993] Proceedings Third Great Lakes Symposium on VLSI-Design Automation of High Performance VLSI Systems.

On the Use of Counters for Reproducing Deterministic Test Sets

Spyros Tragoudas, Amitava Majumdar, Dimitrios Kagaris, 1996, IEEE Trans. Computers.

Von Neumann hybrid cellular automata for generating deterministic test sequences

Spyros Tragoudas, Dimitrios Kagaris, 2001, TODE.

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, PATMOS.

Board-level partitioning for partial scan using fuzzy logic

Kenneth J. Danhof, Spyros Tragoudas, Ralf Münzenberger, 1999, IEEE Trans. Fuzzy Syst..

Diagnosis of segment delay defects with current sensing

Spyros Tragoudas, Themistoklis Haniotakis, Wisam Aljubouri, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Efficient Critical Path Selection Under a Probabilistic Delay Model

Spyros Tragoudas, Ahish Mysore Somashekar, 2017, ACM Great Lakes Symposium on VLSI.

Test set enhancement for quality transition faults using function-based methods

Spyros Tragoudas, Maria K. Michael, Stelios Neophytou, 2005, GLSVLSI '05.

Disjoint Paths with Length Constraints

Spyros Tragoudas, Yaakov L. Varol, 1999, Int. J. Comput. Their Appl..

Error detection encoding for multi-threshold capture mechanism

Spyros Tragoudas, Kedar Karmarkar, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Probabilistic methods for the impact of an SET in combinational logic

Spyros Tragoudas, Sreenivas Gangadhar, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Technical Subcommittees

Naehyuck Chang, Daniela De Venuto, Spyros Tragoudas, 2006, ISQED.

Error correction encoding for multi-threshold capture mechanism

Spyros Tragoudas, Kedar Karmarkar, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

Embedded cores using built-in mechanisms

Spyros Tragoudas, Dimitrios Kagaris, S. Tragoudas, 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

On the nonenumerative path delay fault simulation problem

Spyros Tragoudas, Dimitrios Kagaris, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

The most reliable data path transmission

Spyros Tragoudas, S. Tragoudas, 1999, 1999 IEEE International Performance, Computing and Communications Conference (Cat. No.99CH36305).

Computational analysis of counter-based schemes for VLSI test pattern generation

Spyros Tragoudas, Dimitrios Kagaris, 2001, Discret. Appl. Math..

Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions

Spyros Tragoudas, Edward Flanigan, Arkan Abdulrahman, 2009, 2009 27th IEEE VLSI Test Symposium.

Transmissions in a network with capacities and delays

Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis, 1999, Networks.

Low power test generation for path delay faults using stability functions

Spyros Tragoudas, Mahilchi Milir Vaseekar Kumar, 2005, GLSVLSI '05.

Retiming algorithms with application to VLSI testability

Spyros Tragoudas, Dimitrios Kagaris, 1994, Proceedings of 4th Great Lakes Symposium on VLSI.

Bipartitioning into Overlapping Sets

Spyros Tragoudas, James Haralambides, J. Haralambides, 1995, Int. J. Found. Comput. Sci..

Nanopipelined threshold network synthesis

Spyros Tragoudas, Luke Pierce, S. Tragoudas, 2014, ACM J. Emerg. Technol. Comput. Syst..

The most reliable data-path transmission

Spyros Tragoudas, S. Tragoudas, 2001, IEEE Trans. Reliab..

Computing Disjoint Path with Lenght Constraints

Spyros Tragoudas, Yaakov L. Varol, 1996, WG.

Cellular automata for generating deterministic test sequences

Spyros Tragoudas, Dimitrios Kagaris, S. Tragoudas, 1997, Proceedings European Design and Test Conference. ED & TC 97.

Searching a Solid Pseudo 3-Sided Orthoconvex Grid

Spyros Tragoudas, Antonios Symvonis, 1992, ISAAC.

Delay Analysis for Current Mode Threshold Logic Gate Designs

Spyros Tragoudas, Themistoklis Haniotakis, Chandra Babu Dara, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Exact At-speed Delay Fault Grading in Sequential Circuits

Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi, 2006, 2006 IEEE International Test Conference.

Function-based compact test pattern generation for path delay faults

Spyros Tragoudas, Maria K. Michael, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations

Spyros Tragoudas, Pavan Kumar Javvaji, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parametric fault model for RTD based threshold logic gates

Spyros Tragoudas, Manoj Kumar Goparaju, S. Tragoudas, 2006 .

Partial Scan with Retiming

Spyros Tragoudas, Dimitrios Kagaris, 1993, 30th ACM/IEEE Design Automation Conference.

Minimizing FPGA reconfiguration data at logic level

Haibo Wang, Spyros Tragoudas, Krishna Prasad Raghuraman, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Rewiring for watermarking digital circuit netlists

Spyros Tragoudas, M. Moiz Khan, S. Tragoudas, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Implicit grading of multiple path delay faults

Spyros Tragoudas, Saravanan Padmanaban, 2006, TODE.

Propagation of Transients Along Sensitizable Paths

Spyros Tragoudas, Michael N. Skoufis, Sreenivas Gangadhar, 2008, 2008 14th IEEE International On-Line Testing Symposium.

Techniques to Prioritize Paths for Diagnosis

Spyros Tragoudas, Rajsekhar Adapa, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Generating deterministic unordered test patterns with counters

Spyros Tragoudas, Dimitrios Kagaris, 1996, Proceedings of 14th VLSI Test Symposium.

Enhanced Secure Architecture for Joint Action Test Group Systems

Spyros Tragoudas, Luke Pierce, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

More Efficient Testing of Metal-Oxide Memristor–Based Memory

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Adaptive compressive sensing for low power wireless sensors

Haibo Wang, Spyros Tragoudas, Adam Watkins, 2014, GLSVLSI '14.

A design for testability technique for test pattern generation with LFSRs

Spyros Tragoudas, Dimitrios Kagaris, 1994, Proceedings of IEEE VLSI Test Symposium.

High performance over-the-cell routing

Spyros Tragoudas, Jim E. Crenshaw, Naveed A. Sherwani, 1994, Proceedings of 7th International Conference on VLSI Design.

An efficient heuristic to identify threshold logic functions

Spyros Tragoudas, Ashok Kumar Palaniswamy, S. Tragoudas, 2012, JETC.

A fast nonenumerative automatic test pattern generator for pathdelay faults

Spyros Tragoudas, Dimitrios Karayiannis, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Functions for quality transition fault tests

Spyros Tragoudas, Maria K. Michael, Stelios Neophytou, 2005, Sixth international symposium on quality electronic design (isqed'05).

Timing-Driven Circuit Implementation

Spyros Tragoudas, Dimitrios Karayiannis, 1998, VLSI Design.

Power dissipation component of a management protocol for ad-hoc networks

Spyros Tragoudas, 2000, 2000 IEEE Wireless Communications and Networking Conference. Conference Record (Cat. No.00TH8540).

A Method to Model Statistical Path Delays for Accurate Defect Coverage

Spyros Tragoudas, Pavan Kumar Javvaji, S. Tragoudas, 2018, 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A scalable threshold logic synthesis method using ZBDDs

Spyros Tragoudas, Ashok Kumar Palaniswamy, S. Tragoudas, 2012, GLSVLSI '12.

Efficient identification of (critical) testable path delay faults using decision diagrams

Spyros Tragoudas, Saravanan Padmanaban, S. Tragoudas, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A minimum cut based re-synthesis approach

Haibo Wang, Spyros Tragoudas, M. Welling, 2005, Sixth international symposium on quality electronic design (isqed'05).

ATPG for transition faults of pipelined threshold logic circuits

Spyros Tragoudas, Themistoklis Haniotakis, Ashok Kumar Palaniswamy, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

On the design of optimal counter-based schemes for test set embedding

Spyros Tragoudas, Dimitrios Kagaris, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An analytical method for estimating SET propagation

Spyros Tragoudas, Sreenivas Gangadhar, 2011, 29th VLSI Test Symposium.

Path delay fault testing using test points

Spyros Tragoudas, N. Denny, 2003, TODE.

Uniform area timing-driven circuit implementation

Spyros Tragoudas, Dimitrios Karayiannis, 1995, Proceedings. Fifth Great Lakes Symposium on VLSI.

Using BDDs and ZBDDs for efficient identification of testable path delay faults

Spyros Tragoudas, Saravanan Padmanaban, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Unreachable code identification for improved line coverage

Spyros Tragoudas, Luke Pierce, 2015, Sixteenth International Symposium on Quality Electronic Design.

Gating internal nodes to reduce power during scan shift

Spyros Tragoudas, Rajamani Sethuram, Dheepakkumaran Jayaraman, 2010, GLSVLSI '10.

Low-power multi-core ATPG to target concurrency

Spyros Tragoudas, Arkan Abdulrahman, 2008, Integr..

Implicit deductive fault simulation for complex delay fault models

Spyros Tragoudas, J. V. Deodhar, 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Implementing and clustering modules with complex delays

Spyros Tragoudas, Dimitrios Karayiannis, S. Tragoudas, 1997, Integr..

Threshold Voltage Extraction Using Static NBTI Aging

Spyros Tragoudas, Puneet Ramesh Savanur, 2018, 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A critical path selection method for delay testing

Spyros Tragoudas, Saravanan Padmanaban, 2004, 2004 International Conferce on Test.

Low Power Test Generation for Path Delay Faults

Spyros Tragoudas, Mahilchi Milir Vaseekar Kumar, 2005, J. Low Power Electron..

On-Chip Codeword Generation to Cope With Crosstalk

Spyros Tragoudas, Kedar Karmarkar, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Identification of gates for covering all critical paths

Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu, 2004, Fifth International Workshop on Microprocessor Test and Verification (MTV'04).

On-chip test embedding for multi-weighted random LFSRs

Spyros Tragoudas, Amitava Majumdar, Dimitrios Kagaris, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

Approximate solutions for Graph and Hypergraph Partitioning

Fillia Makedon, Spyros Tragoudas, 1993, Algorithmic Aspects of VLSI Layout.

On the Computation of Fast Data Transmissions in Networks with Capacities and Delays

Spyros Tragoudas, Grammati E. Pantziou, Christos D. Zaroliagis, 1995, WADS.

Low Power Spintronic Ternary Content Addressable Memory

Krishna Prasad Gnawali, Seyed Nima Mozaffari, Spyros Tragoudas, 2018, IEEE Transactions on Nanotechnology.

Exact grading of multiple path delay faults

Spyros Tragoudas, Saravanan Padmanaban, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture

Spyros Tragoudas, Edward Flanigan, Rajsekhar Adapa, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate

Spyros Tragoudas, Themistoklis Haniotakis, Chandra Babu Dara, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

ATPG for Delay Defects in Current Mode Threshold Logic Circuits

Spyros Tragoudas, Themistoklis Haniotakis, Ashok Kumar Palaniswamy, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Adapting an Implicit Path Delay Grading Method for Parallel Architectures

Spyros Tragoudas, Joseph Lenox, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accurate calculation of SET propagation probability for hardening

Spyros Tragoudas, Sreenivas Gangadhar, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Multi-level secure JTAG architecture

Spyros Tragoudas, Luke Pierce, S. Tragoudas, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

Non-enumerative correlation-aware path selection

Spyros Tragoudas, Rathish Jayabharathi, Ahish Mysore Somashekar, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

A method to cope with soft errors

Spyros Tragoudas, Haibo Wang, Michael N. Skoufis, 2007 .

Speedups in embedded systems with a high-performance coprocessor datapath

Spyros Tragoudas, Michalis D. Galanis, Constantinos E. Goutis, 2007, TODE.

Radiation Hardened Latch Designs for Double and Triple Node Upsets

Spyros Tragoudas, Adam Watkins, S. Tragoudas, 2017, IEEE Transactions on Emerging Topics in Computing.

Security enhancement through multiple path transmission in ad hoc networks

Spyros Tragoudas, Themistoklis Haniotakis, Constantinos Kalapodas, 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).

Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements

Spyros Tragoudas, Ahish Mysore Somashekar, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Accelerating DSP applications on a mixed granularity platform with a new reconfigurable coarse-grain data-path

Spyros Tragoudas, Dimitrios Soudris, Michalis D. Galanis, 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

Towards finding path delay fault tests with high test efficiency using ZBDDs

Spyros Tragoudas, Maria K. Michael, Kyriakos Christou, 2005, 2005 International Conference on Computer Design.

Reduced test application time based on reachability analysis

Spyros Tragoudas, Themistoklis Haniotakis, G. Pani, 2005, Sixth international symposium on quality electronic design (isqed'05).

Scalable Offline Searches in DNA Sequences

Spyros Tragoudas, Pragyan P. Mohanty, S. Tragoudas, 2014, JETC.

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels

Spyros Tragoudas, Michalis D. Galanis, George Theodoridis, 2005, J. Circuits Syst. Comput..

CAD Tools for BIST/DFT and Delay Faults

Spyros Tragoudas, 1999, The VLSI Handbook.

Managing the power resources of sensor networks with performance considerations

Spyros Tragoudas, Khadija Stewart, S. Tragoudas, 2007, Comput. Commun..

Low power ATPG for path delay faults

Spyros Tragoudas, Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, 2004, GLSVLSI '04.

River routing and density minimization for channels with interchangeable terminals

Ioannis G. Tollis, Spyros Tragoudas, I. Tollis, 1993, Integr..

Aging-aware critical paths in deep submicron

Spyros Tragoudas, Phaninder Alladi, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

FPGA module minimization

Spyros Tragoudas, D. Kuguris, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

Exact path delay grading with fundamental BDD operations

Spyros Tragoudas, Maria K. Michael, Saravanan Padmanaban, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Pseudoexhaustive TPG with a provably low number of LFSR seeds

Spyros Tragoudas, Dimitrios Kagaris, 2000, Proceedings 2000 International Conference on Computer Design.

A security protocol for sensor networks

Spyros Tragoudas, Themistoklis Haniotakis, Khadija Stewart, 2005, GLOBECOM '05. IEEE Global Telecommunications Conference, 2005..

Design of Scalable Hardware-Efficient Compressive Sensing Image Sensors

Spyros Tragoudas, Haibo Wang, Stefan Leitner, 2018, IEEE Sensors Journal.

An improved algorithm for the generalized min-cut partitioning problem

Spyros Tragoudas, 1994, Proceedings of 4th Great Lakes Symposium on VLSI.

Fast approximation algorithms for multicommodity flow problems

Fillia Makedon, Spyros Tragoudas, Éva Tardos, 1991, STOC '91.

A unified framework for generating all propagation functions for logic errors and events

Spyros Tragoudas, Themistoklis Haniotakis, Maria K. Michael, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Using a WLFSR to embed test pattern pairs in minimum time

Spyros Tragoudas, Dimitrios Kagaris, 2001, Proceedings Seventh International On-Line Testing Workshop.

A fast algorithm for minimizing FPGA combinational and sequential modules

Spyros Tragoudas, Dimitrios Kagaris, S. Tragoudas, 1996, TODE.

A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks

Spyros Tragoudas, Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

VLSI partitioning approximation algorithms based on multicommodity flow and other techniques

Spyros Tragoudas, 1991 .

Non-Enumerative Path Delay Fault Diagnosis

Spyros Tragoudas, Saravanan Padmanaban, 2003, DATE.

A Highly Robust Double Node Upset Tolerant latch

Spyros Tragoudas, Adam Watkins, 2016, 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A method for pseudo-exhaustive test pattern generation

Fillia Makedon, Spyros Tragoudas, Dimitrios Kagaris, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An enhanced analytical electrical masking model for multiple event transients

Spyros Tragoudas, Adam Watkins, 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

Efficient selection of critical paths for delay defects in the presence of process variations

Spyros Tragoudas, Phaninder Alladi, S. Tragoudas, 2016, 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).

Towards Trojan circuit detection with maximum state transition exploration

Spyros Tragoudas, Joseph Lenox, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates

Spyros Tragoudas, Manoj Kumar Goparaju, S. Tragoudas, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Efficient computation of the sensitization probability of a critical path considering process variations and path correlation

Spyros Tragoudas, Pavan Kumar Javvaji, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

Spyros Tragoudas, Maria K. Michael, Kyriakos Christou, 2008, J. Electron. Test..

Non-enumerative generation of statistical path delays for ATPG

Spyros Tragoudas, Sreenivas Gangadhar, Rathish Jayabharathi, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Delay considerations in testing and synthesis of integrated circuits

Spyros Tragoudas, Dimitrios Karayiannis, 1996 .

Scan Shift Power Reduction by Gating Internal Nodes

Spyros Tragoudas, Rajamani Sethuram, Dheepakkumaran Jayaraman, 2010, J. Low Power Electron..

Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection

Spyros Tragoudas, Sreenivas Gangadhar, Rathish Jayabharathi, 2016, TODE.

CAD DFT and Test Architectures

Spyros Tragoudas, Nick Kanopoulos, Dimitri Kagaris, 2006 .

An ILP based management protocol for wireless networks

Spyros Tragoudas, Khadija Stewart, 2005 .

High-Speed Memristive Ternary Content Addressable Memory

Krishna Prasad Gnawali, Spyros Tragoudas, 2021 .

A Fault Model to Detect Design Errors in Combinational Circuits

Spyros Tragoudas, Puneet Ramesh Savanur, 2021, 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Developing Benchmarks for Radiation Testing of Microcontroller Arithmetic Units Using ATPG

Spyros Tragoudas, Heather M. Quinn, Krishna P. Gnawali, 2021, IEEE Transactions on Nuclear Science.

Efficient identification of (critical) testable path delay faults using decision diagrams

Spyros Tragoudas, S. Padmanaban, 2005 .

Reducing power, area, and delay of threshold logic gates considering non-integer weights

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).