Kyoichiro Asayama

Bipolar CMOS-merged technology for a high-speed 1-Mbit DRAM

Kiyoo Itoh, Goro Kitsukawa, Ryoichi Hori, 1989 .

An experimental 1-Mbit BiCMOS DRAM

Kiyoo Itoh, Takayuki Kawahara, Takao Watanabe, 1987 .

An experimental 35ns 1Mb biCMOS DRAM

Takayuki Kawahara, Kiyoo Itoh, Yoshiki Kawajiri, 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

Toshiaki Yamanaka, Katsuro Sasaki, Sadayuki Morita, 1994 .