Nan-Chi Chou

发表

Jianhua Liu, Chung-Kuan Cheng, Michael Chang, 2004, FPGA '04.

Unified quadratic programming approach for mixed mode placement

Chung-Kuan Cheng, Bo Yao, Nan-Chi Chou, 2005, ISPD '05.

Performance-driven partitioning using retiming and replication

Chung-Kuan Cheng, Nan-Chi Chou, Walter H. Ku, 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

Circuit Partitioning for Huge Logic Emulation Systems

Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, 1994, 31st Design Automation Conference.

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications

Evangeline F. Y. Young, Ronald L. Graham, Chung-Kuan Cheng, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

An optimal probe testing algorithm for the connectivity verification of MCM substrates

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Hu, 1992, ICCAD.

A practical cut-based physical retiming algorithm for field programmable gate arrays

Dongsheng Wang, Nan-Chi Chou, Peter Suaris, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

The effect of post-layout pin permutation on timing

Nan-Chi Chou, Peter Suaris, Yuzheng Ding, 2005, FPGA '05.

Dynamic probe scheduling optimization for MCM substrate test

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Russell, 1994 .

A practical cut-based physical retiming algorithm for field programmable gate arrays

Dongsheng Wang, Nan-Chi Chou, Peter Suaris, 2005, ASP-DAC '05.

Optimal Test Size and Efficient Probe Scheduling for Substrate Verification Using Two-Probe Testers

Chung-Kuan Cheng, Nan-Chi Chou, 1993 .

Incremental physical resynthesis for timing optimization

Nan-Chi Chou, Peter Suaris, Lung-Tien Liu, 2004, FPGA '04.

An optimal probe testing algorithm for the connectivity verification of MCM substrates

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Hu, 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

On general zero-skew clock net construction

Chung-Kuan Cheng, Nan-Chi Chou, 1995, IEEE Trans. Very Large Scale Integr. Syst..

The application of hierarchical trees to circuit partitioning, clock net routing, and connectivity verification problems

Nan-Chi Chou, 1993 .

Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications

Bill Salefski, Chung-Kuan Cheng, Nan-Chi Chou, 2009, 2009 46th ACM/IEEE Design Automation Conference.

High-performance microelectronic substrate verification using probe testers

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Russell, 1992, [1992] Proceedings. Fifth Annual IEEE International ASIC Conference and Exhibit.

Improving the efficiency of static timing analysis with false paths

Yi Zhu, Shuo Zhou, Chung-Kuan Cheng, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Local ratio cut and set covering partitioning for huge logic emulation systems

Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A multi-probe approach for MCM substrate testing

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Hu, 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An Algebraic Multigrid Solver for Analytical with Layout Based Clustering Placement

Bo Yao, Andrew B. Kahng, John F. MacDonald, 2003 .

Efficient Timing Analysis With Known False Paths Using Biclique Covering

Yi Zhu, Shuo Zhou, Chung-Kuan Cheng, 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages

Dongsheng Wang, Nan-Chi Chou, Peter Suaris, 2003, PATMOS.

A multi-chip module substrate testing algorithm

Chung-Kuan Cheng, Nan-Chi Chou, T. C. Hu, 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

An algebraic multigrid solver for analytical placement with layout based clustering

Andrew B. Kahng, Chung-Kuan Cheng, Bo Yao, 2003, DAC '03.