Ricardo Reis

发表

AnAlgorithm forI/OPartitioning Targeting 3D Circuits and ItsImpact on 3D-Vias

Renato Fernandes Hentschke, Sandro Sawicki, Marcelo Johann, 2006 .

Gate Sizing Minimizing Delay and Power/Area

Guilherme Flach, Gracieli Posser, Gustavo Wilke, 2011 .

An Efficient Layout Style for Three Metal CMOS Macro-Cells

Fernando Moraes, Ricardo Reis, F. Lima, 1997 .

Statistical analysis of hold time violations

Rajeev Murgai, William W. Walker, Ricardo Reis, 2010 .

Specification and design of an Ethernet interface soft IP

Sergio Bampi, Ricardo Reis, Juergen Rochol, 1999, Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387).

Distributed system-level design using pair-programming over Cave

Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, 2001 .

Prematurely Aborting Linear System Solver in Quadratic Placement

Guilherme Flach, Marcelo Johann, Ricardo Reis, 2011 .

Fault Tolerance in Programmable Circuits

Fernanda Lima Kastensmidt, Ricardo Reis, 2007 .

Fast interconnect parasitic extraction in deep submicron using bin-based algorithm

Fernando Moraes, Ricardo Reis, F. K. Ferreira, 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

Hierarchical circuit extractor

Ricardo Reis, Marcos Augusto Stemmer, 1990, Other Conferences.

Associating CMOS transistors with BDD arcs for technology mapping

Ricardo Reis, D. Auvergne, Andre I. Reis, 1995 .

Gate sizing using geometric programming

Guilherme Flach, Gracieli Posser, Gustavo Wilke, 2012 .

Design of RegularLayouts toImprove Predictability

Ricardo Reis, Cláudio Leonardo Montassieur de Menezes, Cristina Meinhardt, 2006 .

Providing Flexible Internet Infrastructure for FPGA-Based CAD Courses

Leandro Soares Indrusiak, Manfred Glesner, Ricardo Reis, 2000 .

Supporting collaboration in distributed design environments using a shared object space infrastructure

Leandro Soares Indrusiak, Manfred Glesner, Sandro Sawicki, 2004 .

A low device occupation IP to implement Rijndael algorithm

Ricardo Reis, Alex Panato, Marcelo Barcelos, 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS

Sachin S. Sapatnekar, Gracieli Posser, Ricardo Reis, 2016 .

Simultaneous Gate Sizing and Vth Assignment Simultaneous Gate Sizing and Vth Assignment using Lagrangian Relaxation and Delay using Lagrangian Relaxation and Delay

Guilherme Flach, Tiago Reimann, Gracieli Posser, 2013 .

Computational infrastructure for the collaborative design of integrated systems over a distributed environment

Leandro Soares Indrusiak, Manfred Glesner, Ricardo Reis, 2003 .

Geração automática de leiaute de portas CMOS complexas

Ricardo Reis, Andre I. Reis, Carlos Henrique Gustavo Hassmann, 1998 .

Desenvolvimento de um conversor para viabilizar a síntese de circuitos integrados a partir de uma descrição VHDL

Ricardo Reis, Andre L.L. Serpa, Fernanda Gusmao de Lima, 1998 .

An event-based consistency control mechanism for collaborative design using reflection techniques

Leandro Soares Indrusiak, Manfred Glesner, Ricardo Reis, 2004 .

Collaborative learning by sharing design experience

Leandro Soares Indrusiak, Manfred Glesner, Ricardo Reis, 2002 .

UML-driven design space delimitation and exploration : a case study on networks-on-chip

Leandro Soares Indrusiak, Altamiro Amadeu Susin, Manfred Glesner, 2004 .

An efficient design methodology for standard cell circuits

Marcelo Lubaszewski, Ricardo Reis, R. Gomes, 1988, 1988., IEEE International Symposium on Circuits and Systems.

INTEGRITY, RELIABILITY & FAILURE IN REFRIGERATION SYSTEMS FOR DRAUGHT DRINKS

João S. Fernandes, Joaquim Gabriel, Ricardo Reis, 2013 .

Homero – Um Editor VHDL Cooperativo via Web

Leandro Soares Indrusiak, Sandro Sawicki, Ricardo Reis, 2001 .

On the integration of uml sequence diagrams and actor-oriented simulation models

Leandro Soares Indrusiak, Manfred Glesner, Ricardo Reis, 2005 .

Interconnection length estimation at logic-level

Ricardo Reis, Fernando Moraes, João Baptista Martins, 2001, Symposium on Integrated Circuits and Systems Design.

Pre-layout performance prediction for automatic macro-cell synthesis

Lionel Torres, Michel Robert, Daniel Auvergne, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.