Shashank Raghuraman

Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA

Amit Acharyya, Swati Bhardwaj, Shashank Raghuraman, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Coordinate rotation and vector cross product based hardware accelerator for nD FastICA

Amit Acharyya, Swati Bhardwaj, Shashank Raghuraman, 2017, 2017 European Conference on Circuit Theory and Design (ECCTD).

Coordinate Rotation-Based Low Complexity $K$ -Means Clustering Architecture

Koushik Maharatna, Amit Acharyya, Dwaipayan Biswas, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low complexity hardware accelerator for nD FastICA based on coordinate rotation

Amit Acharyya, Swati Bhardwaj, Shashank Raghuraman, 2017, 2017 IEEE International Workshop on Signal Processing Systems (SiPS).

Vector Cross Product and Coordinate Rotation Based nD Hybrid FastICA

Amit Acharyya, Swati Bhardwaj, Shashank Raghuraman, 2018, J. Low Power Electron..

Impact of System-on-Chip Integration of AEAD Ciphers

Leyla Nazhandali, Shashank Raghuraman, L. Nazhandali, 2020, IACR Cryptol. ePrint Arch..

Efficiency of Logic Minimization Techniques for Cryptographic Hardware Implementation

Shashank Raghuraman, Shashank Raghuraman, 2019 .