Susumu Imaoka

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Koji Nii, Hironori Akamatsu, Toshiyuki Oashi, 2008, IEEE Journal of Solid-State Circuits.

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Koji Nii, Yuji Oda, Koichiro Ishibashi, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

Koji Nii, Hiroshi Makino, Hironori Akamatsu, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

Koji Nii, Yuji Oda, Koichiro Ishibashi, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.