Mitsuru Aniya

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, ${-}$ 98 dB THD, and 79 dB SNDR

Gabor C. Temes, Koichi Hamashita, Kaoru Takasuka, 2008, IEEE Journal of Solid-State Circuits.

A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR

Gabor C. Temes, Koichi Hamashita, Kaoru Takasuka, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer

Koichi Hamashita, Un-Ku Moon, Seiji Takeuchi, 2011, IEEE Journal of Solid-State Circuits.

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Koichi Hamashita, Un-Ku Moon, Seiji Takeuchi, 2010, IEEE Journal of Solid-State Circuits.

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application

Pavan Kumar Hanumolu, Gabor C. Temes, Koichi Hamashita, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer

Pavan Kumar Hanumolu, Gabor C. Temes, Koichi Hamashita, 2010, IEEE Custom Integrated Circuits Conference 2010.

A Noise-Coupled Time-Interleaved Delta-Sigma ADC with 4 . 2 MHz BW ,-98 dB THD , and 79 dB SNDR

Gabor C. Temes, Koichi Hamashita, Kaoru Takasuka, 2008 .