C. Verove

Demonstration of an extendable and industrial 300mm BEOL integration for the 65-nm technology node

D. Reber, A. Farcy, C. Cregut, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

Plasma treatments to improve line-width roughness during gate patterning

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2013 .

Plasma treatment to improve linewidth roughness during gate patterning

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2012, Advanced Lithography.

Dual damascene architectures evaluation for the 0.18 /spl mu/m technology and below

E. Sabouret, M. Guillermet, C. Verove, 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).

Unbiased line width roughness measurements with critical dimension scanning electron microscopy and critical dimension atomic force microscopy

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2012 .

Benefits of plasma treatments on critical dimension control and line width roughness transfer during gate patterning

Olivier Joubert, Marc Fouchier, Erwine Pargon, 2013 .

Electron-shading characterization in a HDP contact etching process using a patterned CHARM wafer

G. Reimbold, M. Haond, W. Lukaszek, 2000, 2000 5th International Symposium on Plasma Process-Induced Damage (IEEE Cat. No.00TH8479).