K. Balakrishnan

SOI FinFET versus bulk FinFET for 10nm and below

Xin Sun, Terence B. Hook, E. Nowak, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Crash analysis of a conceptual electric vehicle with a damage tolerant battery pack

Thomas Siegmund, Waterloo Tsutsui, Weinong Chen, 2016 .

Application study of innovative Quality Circle Programme and its Decision Support System in a gear manufacturing company

S. R. Devadasan, S. Vinodh, K. Balakrishnan, 2009 .

Advanced 3D Monolithic hybrid CMOS with Sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs

P. Hashemi, D. Caimi, L. Czornomaz, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

High-performance Si1−xGex channel on insulator trigate PFETs featuring an implant-free process and aggressively-scaled fin and gate dimensions

R. H. Dennard, E. Leobandung, P. Hashemi, 2013, 2013 Symposium on VLSI Technology.

Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths

T. Ando, V. Narayanan, E. Leobandung, 2016, 2016 IEEE Symposium on VLSI Technology.

Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond

I. Lauer, R. L. Bruce, K. Balakrishnan, 2013, 2013 IEEE International Electron Devices Meeting.

Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices

S. Narasimha, T. Yamashita, H. Bu, 2013, 2013 Symposium on VLSI Technology.