M. Caymax

发表

2D materials: roadmap to CMOS integration

C. Huyghebaert, A. Leonhardt, D. Lin, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Comparison of sub 1 nm TiN/HfO/sub 2/ with poly-Si/HfO/sub 2/ gate stacks using scaled chemical oxide interface

S. De Gendt, M. Heyns, M. Caymax, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

R. Degraeve, D. Lin, N. Collaert, 2012, 2012 International Electron Devices Meeting.

Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.

R. Rooyackers, G. Eneman, S. Biesemans, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Low temperature deposition of 2D WS2 layers from WF6 and H2S precursors: impact of reducing agents.

S. De Gendt, S. Van Elshocht, H. Bender, 2015, Chemical communications.

Thermally insulated structures for IR bolometers, made of polycrystalline silicon germanium alloys

P. Fiorini, S. Sedky, M. Caymax, 1997, Proceedings of International Solid State Sensors and Actuators Conference (Transducers '97).

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

R. Rooyackers, N. Collaert, G. Eneman, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Influence of the Ge-concentration and RTA on the device performance of strained Si/SiGe pMOS devices

N. Collaert, P. Verheyen, M. Caymax, 2002, 32nd European Solid-State Device Research Conference.

Impact of Epi-Si growth temperature on Ge-pFET performance

B. Kaczer, G. Hellings, J. Mitard, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to $\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}$ and InP Capacitors

A. Alian, G. Brammertz, M. Meuris, 2011, IEEE Transactions on Electron Devices.

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

R. Rooyackers, N. Collaert, S. Biesemans, 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

A 50 nm vertical Si/sub 0.70/Ge/sub 0.30//Si/sub 0.85/Ge/sub 0.15/ pMOSFET with an oxide/nitride gate dielectric

M. Van Rossum, N. Collaert, K. De Meyer, 2001, 2001 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers (Cat. No.01TH8517).

Scaling of high-k dielectrics towards sub-1nm EOT

S. De Gendt, D. Pique, S. Van Elshocht, 2003, 2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).

Oxide Trapping in the InGaAs–$\hbox{Al}_{2} \hbox{O}_{3}$ System and the Role of Sulfur in Reducing the $ \hbox{Al}_{2}\hbox{O}_{3}$ Trap Density

R. Degraeve, C. Merckling, Dennis Lin, 2012, IEEE Electron Device Letters.

Performance comparison of sub 1 nm sputtered TiN/HfO/sub 2/ nMOS and pMOSFETs

S. De Gendt, L. Pantisano, A. Kerber, 2003, IEEE International Electron Devices Meeting 2003.

Diffusion length measurements on plasma-sprayed polycrystalline silicon substrates and on silicon grown on them by chemical vapour deposition

M. Rodot, G. Brun, M. Caymax, 1987 .

Characterization of bolometers based on polycrystalline silicon germanium alloys

P. Fiorini, L. Hermans, S. Sedky, 1998, IEEE Electron Device Letters.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

C. Merckling, D. Lin, N. Waldron, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Challenges for introducing Ge and III/V devices into CMOS technologies

B. Kaczer, G. Hellings, L. Witters, 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).