T. Levin

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

Failure Isolation in Ring Oscillator Circuit and Defect Detection in CMOS Technology Research

K. Cheng, J. Strane, T. Levin, 2019, 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.

Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS

T. Nagumo, N. Loubet, W. Schwarzenbach, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Bottom oxidation through STI (BOTS) — A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

P. Oldiges, B. Haran, H. Bu, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Aggressively scaled strained silicon directly on insulator (SSDOI) FinFETs

Pierre Morin, Frederic Allibert, Nicolas Loubet, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node

O. Faynot, Y. Escarabajal, B. Lherron, 2014, 2014 IEEE International Electron Devices Meeting.

Impact of back bias on ultra-thin body and BOX (UTBB) devices

M. Vinet, T. Skotnicki, L. Grenouillet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

Yongan Xu, Yunpeng Yin, Chiew-seng Koay, 2012, 2012 IEEE International Interconnect Technology Conference.