J. O'Neill

Sub-25nm FinFET with advanced fin formation and short channel effect engineering

K. Maitra, P. Kulkarni, T. Yamashita, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

B. Jagannathan, N. Loubet, P. Kulkarni, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell

N. Loubet, P. Kulkarni, H. Bu, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

Extremely thin SOI (ETSOI) technology: Past, present, and future

P. Kulkarni, H. Bu, A. Khakifirooz, 2010, 2010 IEEE International SOI Conference (SOI).

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

K. Maitra, T. Yamashita, V. S. Basker, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch

K. Maitra, P. Kulkarni, T. Yamashita, 2010, 2010 Symposium on VLSI Technology.