Tsai-Ming Hsieh

发表

Partition-based Routing Tree Algorithm with Obstacles

Yu-Cheng Lin, Hui-Yu Huang, Hsin-Hsiung Huang, 2007, 2007 International Symposium on Integrated Circuits.

A new congestion and crosstalk aware router

Tsai-Ming Hsieh, Chin-Hui Wang, Yung-Ching Chen, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Obstacle-avoiding electromigration aware wire planning for analog circuits

Hsin-Hsiung Huang, Tsai-Ming Hsieh, Cheng-Chiang Lin, 2009, Proceedings of the 2009 12th International Symposium on Integrated Circuits.

Structural decomposition with functional considerations for low power

Yu-Chung Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh, 2002, Proceedings International Symposium on Quality Electronic Design.

Technology remapping for engineering change with wirelength consideration

Tsai-Ming Hsieh, Jui-Hung Hung, Yao-Kai Yeh, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

X-architecture obstacles-avoiding routing with ECO consideration

Hsin-Hsiung Huang, Tsai-Ming Hsieh, Yu-Cheng Lin, 2010 .

Industry-based Training Course for Line Following Maze Robot Implementation

Juing-Huei Su, Hsin-Hsiung Huang, Tsai-Ming Hsieh, 2010 .

Timing-driven obstacles-avoiding routing tree construction for a multiple-layer system

Yu-Cheng Lin, Hui-Yu Huang, Hsin-Hsiung Huang, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Timing-driven X-architecture router among rectangular obstacles

Shu-Ping Chang, Yu-Cheng Lin, Hsin-Hsiung Huang, 2008, 2008 IEEE International Symposium on Circuits and Systems.

Image Retrieval based on color and texture features

Tsai-Ming Hsieh, Mohd Helmy Abd Wahab, Chin-Hung Su, 2012, 2012 9th International Conference on Fuzzy Systems and Knowledge Discovery.

Sequence-pair based placement with boundary constraints

Tsai-Ming Hsieh, Chih-Hung Lee, Yi-Lin Hsieh, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Crosstalk Minimization in Non-Manhattan Channel Routing

Tsai-Ming Hsieh, Ying-Chih Chen, 1999 .

A new ECO technology for functional changes and removing timing violations

Tsai-Ming Hsieh, Jui-Hung Hung, Yao-Kai Yeh, 2011, 2011 12th International Symposium on Quality Electronic Design.

A logic difference generator with spare cells consideration for ECO synthesis

Yu-Cheng Lin, Tsai-Ming Hsieh, Wei-Kai Cheng, 2015, Sixteenth International Symposium on Quality Electronic Design.

Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint

Yu-Chung Lin, Tsai-Ming Hsieh, Yi-Ling Hsieh, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Unified approach for simultaneous functional and timing ECO

Yu-Cheng Lin, Tsai-Ming Hsieh, Wei-Kai Cheng, 2016, IET Circuits Devices Syst..

Cost minimization of partitioned circuits with complex resource constraints in FPGAs (poster abstract)

Yu-Chung Lin, Tsai-Ming Hsieh, Su-Feng Tseng, 2000, FPGA '00.

Clock Network Power Saving Using Multi-Bit Flip-Flops in Multiple Voltage Island Design

Tsai-Ming Hsieh, Yu-Cheng Lin, Li-Wei Huang, 2013 .

An efficient hierarchical approach for general floorplan area minimization

Tsai-Ming Hsieh, Chih-Hung Lee, Wen-Yu Fu, 2002, Asia-Pacific Conference on Circuits and Systems.

The Implementation of a Line Following Maze Robot for Mobile Robot System Courses

Juing-Huei Su, Hsin-Hsiung Huang, Tsai-Ming Hsieh, 2009 .

Clock tree construction using gated clock cloning

Tsai-Ming Hsieh, Hsin-Hung Chang, Jui-Hung Hung, 2012, 2012 4th Asia Symposium on Quality Electronic Design (ASQED).

EngineeringChange Order-Driven Routing Tree Construction

Yu-Cheng Lin, Hsin-Hsiung Huang, Tsai-Ming Hsieh, 2009 .

Performance-Driven Global Routing in the Present of Obstacles

Tsai-Ming Hsieh, Hsin-Hsiung Huang, Wei-Yu Wu, 2006 .

Timing- and interference-free multi-layer routing tree

Hsin-Hsiung Huang, Tsai-Ming Hsieh, Pi-Hua Su, 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

Minimum crosstalk channel routing with dogleg

Yu-Chung Lin, Tsai-Ming Hsieh, Po-Xun Chiu, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Interconnect-driven multistage hierarchical floorplanning for soft modules

Tsai-Ming Hsieh, Chih-Hung Lee, Wen-Yu Fu, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

Congestion-driven floorplanning by adaptive modular shaping

Hsin-Hsiung Huang, Tsai-Ming Hsieh, Chih-Yuan Lin, 2005, 48th Midwest Symposium on Circuits and Systems, 2005..

An adaptive algorithm for computing the initial states of retimed circuits

Yu-Chung Lin, Tsai-Ming Hsieh, Wen-Ling Chen, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

A new effective congestion model in floorplan design

Tsai-Ming Hsieh, Yi-Lin Hsieh, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Optimal Supply Voltage Assignment under Timing, Power and Area Constraints

Hsin-Hsiung Huang, Tsai-Ming Hsieh, Cheng-Chiang Lin, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Optimal voltage assignment approach for low power using ILP

Hsin-Hsiung Huang, Tsai-Ming Hsieh, Cheng-Chiang Lin, 2008 .

A congestion-driven buffer planner with space reservation

Hsin-Hsiung Huang, Tsai-Ming Hsieh, Yung-Ching Chen, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Optical Proximity Correction Using a New Hyper Error Estimation Method

Yu-Cheng Lin, Tsai-Ming Hsieh, Jui-Hung Hung, 2013 .

Minimum cost complex resource FPGA partition with performance refining

Tsai-Ming Hsieh, Chih-Hung Lee, Yu-Shan Hung, 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

Floorplanning with clock tree estimation

Shih-Hsu Huang, Tsai-Ming Hsieh, Chih-Yuan Lin, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A new formulation for SOC floorplan area minimization problem

Yu-Chung Lin, Tsai-Ming Hsieh, Chih-Hung Lee, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Wire Planning for Electromigration and Interference Avoidance in Analog Circuits

Hsin-Hsiung Huang, Tsai-Ming Hsieh, Cheng-Chiang Lin, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Cost minimization of partitioning circuits with complex resource constraints in FPGAs

Tsai-Ming Hsieh, Su-Fen Tseng, T. Hsieh, 2000, IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394).

Some Relationships Between Certain Families of Ordinary and Fractional Differential Equations

Hari M. Srivastava, Tsai-Ming Hsieh, Shy-Der Lin, 2003 .

Timing-driven non-rectangular obstacles-avoiding routing algorithm for the X-architecture

Shu-Ping Chang, Hsin-Hsiung Huang, Tsai-Ming Hsieh, 2009 .