Harris E. Michail

发表

Area-Throughput Trade-Offs for SHA-1 and SHA-256 Hash Functions' Pipelined Designs

George Athanasiou, Thanos Stouraitis, George Theodoridis, 2016, J. Circuits Syst. Comput..

Priority Handling Aggregation Technique (PHAT) for Wireless Sensor Networks

Dimitris Tsitsipis, Stavros A. Koubias, Christos Panagiotou, 2012, Proceedings of 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation (ETFA 2012).

Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2010, J. Signal Process. Syst..

Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers

Dimitrios Soudris, George Theodoridis, Athanasios Kakarountas, 2006, J. Low Power Electron..

Distribution of Cultural Content through Exploitation of Cryptographic Algorithms and Hardware Identification

Marinos Ioannides, Harris E. Michail, Dimitris Gavrilis, 2014, EuroMed.

Driver workload analysis using an interactive 3D driving simulator.

Maria Pampaka, Despina Michael, Harris E. Michail, 2013 .

Novel Hardware Implementation of the Cipher Message Authentication Code

Michalis D. Galanis, Constantinos E. Goutis, Harris E. Michail, 2008, J. Comput. Networks Commun..

Design and validation of an agent-based driving simulator

Maria Pampaka, Harris E. Michail, Andreas Gregoriades, 2018, SummerSim.

Ultra high speed SHA-256 hashing cryptographic module for IPSec hardware/software codesign

George Athanasiou, Constantinos E. Goutis, Harris E. Michail, 2010, 2010 International Conference on Security and Cryptography (SECRYPT).

High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications

George Theodoridis, Constantinos E. Goutis, Athanasios Kakarountas, 2006, The Journal of Supercomputing.

A Top-Down Design Methodology for Ultrahigh-Performance Hashing Cores

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2009, IEEE Transactions on Dependable and Secure Computing.

VLSI design and implementation of reconfigurable cryptographic systems for symmetric encryption

Odysseas G. Koufopavlou, Harris E. Michail, Georgios N. Selimis, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

Authentication with RIPEMD-160 and Other Alternatives: A Hardware Design Perspective

Harris E. Michail, Angeliki Kritikakou, Constantinos E. Goutis, 2010 .

Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2005, PATMOS.

Designs and comparisons of authentication modules for IPSec in configurable and extensible embedded processor

George Athanasiou, Constantinos E. Goutis, Harris E. Michail, 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.

Evolution of the e-Museum Concept through Exploitation of Cryptographic Algorithms

George Athanasiou, Marinos Ioannides, Harris E. Michail, 2012, EuroMed.

High performance pipelined FPGA implementation of the SHA-3 hash algorithm

Artemios G. Voyiatzis, Harris E. Michail, Lenos Ioannou, 2015, 2015 4th Mediterranean Conference on Embedded Computing (MECO).

Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2009, IET Comput. Digit. Tech..

A data locality methodology for matrix–matrix multiplication algorithm

George Athanasiou, Constantinos E. Goutis, Harris E. Michail, 2010, The Journal of Supercomputing.

Pipelined SHA-3 Implementations on FPGA: Architecture and Performance Analysis

Artemios G. Voyiatzis, Harris E. Michail, Lenos Ioannou, 2015, CS2@HiPEAC.

Assessing Students' Learning in MIS using Concept Mapping

Maria Pampaka, Harris E. Michail, Andreas Gregoriades, 2009, J. Inf. Syst. Educ..

An Intelligent Transportation System for Accident Risk Index Quantification

Kyriacos C. Mouskos, Harris E. Michail, Andreas Gregoriades, 2012, ICEIS.

On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2012, SECRYPT.

Optimising the SHA-512 cryptographic hash function on FPGAs

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2013, IET Comput. Digit. Tech..

Cipher Block Based Authentication Module: a Hardware Design Perspective

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2011, J. Circuits Syst. Comput..

High-performance FPGA implementations of the cryptographic hash function JH

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2013, IET Comput. Digit. Tech..

High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2012, SECRYPT.

A low-power and high-throughput implementation of the SHA-1 hash function

Constantinos E. Goutis, Athanasios Kakarountas, Odysseas G. Koufopavlou, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Efficient FPGA Implementation of Novel Cryptographic Hashing Core

Harris E. Michail, Constantinos E. Goutis, A. P. Kakarountas, 2006 .

Hardware implementation of the Totally Self-Checking SHA-256 hash core

George Athanasiou, Constantinos E. Goutis, Athanasios Kakarountas, 2015, IEEE EUROCON 2015 - International Conference on Computer as a Tool (EUROCON).

On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2014, Integr..

High-throughput implementation of the RIPEMD-160

Harris E. Michail, Costas E. Goutis, Abdoul Rjoub, 2009 .

A driving simulator for discovering requirements in complex systems

Maria Pampaka, Harris E. Michail, Andreas Gregoriades, 2015, SummerSim.

Novel high throughput implementation of SHA-256 hash function through pre-computation technique

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

High Throughput Hardware/Software Co-Design Approach for SHA-256 Hashing Cryptographic Module In IPSec/IPv6

Harris E. Michail, Constantinos E. Goutis, Andreas Gregoriades, 2010 .

Throughput/Area Trade-Offs of Loop-Unrolling, Functional and Structural Pipeline for Skein Hash Function

George Athanasiou, George Theodoridis, Harris E. Michail, 2013 .

Efficient Pipelined Hardware Implementation of RIPEMD-160 Hash Function

Harris E. Michail, Constantinos E. Goutis, A. P. Kakarountas, 2008 .

An RNS Implementation of an $F_{p}$ Elliptic Curve Point Multiplier

Thanos Stouraitis, Athanasios Kakarountas, Apostolos P. Fournaris, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2013, J. Circuits Syst. Comput..

Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures

George Athanasiou, George Theodoridis, Constantinos E. Goutis, 2016, Microprocess. Microsystems.

High-level safety mechanisms for safety-critical application-specific low power devices

Spiridon Nikolaidis, Harris E. Michail, V. Kokkinos, 2005 .

A Methodology for Speeding Up Fast Fourier Transform Focusing on Memory Architecture Utilization

George Athanasiou, Constantinos E. Goutis, Nikolaos S. Alachiotis, 2011, IEEE Transactions on Signal Processing.

Server side hashing core exceeding 3 Gbps of throughput

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2007, Int. J. Secur. Networks.

A Robotic System for Home Security Enhancement

Despina Michael, Harris E. Michail, Andreas Gregoriades, 2010, ICOST.

Efficient implementation of the keyed-hash message authentication code (HMAC) using the SHA-1 hash function

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2004, Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004..

Improved throughput bit-serial multiplier for GF(2m) fields

Apostolos P. Fournaris, Odysseas G. Koufopavlou, Harris E. Michail, 2009, Integr..

A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy

Constantinos E. Goutis, Athanasios Kakarountas, Harris E. Michail, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Implementation of HSSec: a high-speed cryptographic co-processor

Constantinos E. Goutis, Athanasios Kakarountas, Costas Efstathiou, 2007, 2007 IEEE Conference on Emerging Technologies and Factory Automation (EFTA 2007).