Luc Rijnders

Timing optimization by bit-level arithmetic transformations

Hugo De Man, Luc Rijnders, Zohair Sahraoui, 1995, Proceedings of EURO-DAC. European Design Automation Conference.

MPEG-4 Video Decoder

Luc Rijnders, Miroslav Cupak, 2005 .

REDUSA: module generation by automatic elimination of superfluous blocks in regular structures

Hugo De Man, Luc Rijnders, Paul Six, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A hardware virtual machine for networked reconfiguration

Hugo De Man, Yajun Ha, Patrick Schaumont, 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).

OCAPI-XL Based Approach

Luc Rijnders, Miroslav Cupak, 2005 .

A methodology and design environment for DSP ASIC fixed point refinement

Patrick Schaumont, Luc Rijnders, Serge Vernalde, 1999, DATE '99.

Towards high performance sub-10nm finW bulk FinFET technology

Naoto Horiguchi, Jérôme Mitard, P. Eyben, 2016, 2016 46th European Solid-State Device Research Conference (ESSDERC).

Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications

Patrick Schaumont, Marc Engels, Luc Rijnders, 1997, Proceedings European Design and Test Conference. ED & TC 97.

REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures

Hugo De Man, Luc Rijnders, Paul Six, 1989, 26th ACM/IEEE Design Automation Conference.

A programming environment for the design of complex high speed ASICs

Patrick Schaumont, Marc Engels, Luc Rijnders, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java

Rudy Lauwereins, Diederik Verkest, Francky Catthoor, 2003, SCOPES.

System Level Architecture Exploration for Reconfigurable Systems On Chip

Yang Qu, Kostas Masselos, Nikos S. Voros, 2006, 2006 International Conference on Field Programmable Logic and Applications.