Bernard N. Sheehan

发表

Library compatible C/sub eff/ for gate-level timing

Bernard N. Sheehan, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Predicting coupled noise in RC circuits

Bernard N. Sheehan, 2000, DATE '00.

ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization

Bernard N. Sheehan, 1999, DAC '99.

Higher Order Orthogonal Iteration of Tensors (HOOI) and its Relation to PCA and GLRAM

Yousef Saad, Bernard N. Sheehan, Y. Saad, 2007, SDM.

Osculating Thevenin model for predicting delay and slew of capacitively characterized cells

Bernard N. Sheehan, 2002, DAC '02.

Library Compatible Ceff for Gate-Level Timing

Bernard N. Sheehan, 2002, DATE.

An AWE technique for fast printed circuit board delays

Bernard N. Sheehan, B. Sheehan, 1996, 33rd Design Automation Conference Proceedings, 1996.

Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments

Bernard N. Sheehan, 2000, Proceedings 37th Design Automation Conference.

Branch Merge Reduction of RLCM Networks

Bernard N. Sheehan, 2003, ICCAD 2003.

Projective convolution: RLC model-order reduction using the impulse response

Bernard N. Sheehan, 1999, DATE '99.

TICER: Realizable reduction of extracted RC circuits

Bernard N. Sheehan, B. Sheehan, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Realizable Reduction of $RC$ Networks

Bernard N. Sheehan, B. Sheehan, 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Branch Merge Reduction of RLCM Networks

Bernard N. Sheehan, 2003, ICCAD.

Realizable reduction of passive networks

Sachin S. Sapatnekar, Yousef Saad, Bernard N. Sheehan, 2005 .