Tohru Nakamura

Shallow p-Type Layers in Si by Rapid Vapor-Phase Doping for High-Speed Bipolar and MOS Applications (Special Issue on Ultra-High-Speed LSIs)

Seiji Suzuki, Yukihiro Kiyota, Tohru Nakamura, 1996 .

A 36 kb/2 ns RAM with 1 kG/100 ps logic gate array

Satoru Isomura, Kunihiko Yamaguchi, Katsumi Ogiue, 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.