Wei Wing Mar

A 22nm 2.5MB slice on-die L3 cache for the next generation Xeon® Processor

Wei Chen, Szu-Liang Chen, Siufu Chiu, 2013, 2013 Symposium on VLSI Circuits.

A 45nm 24MB on-die L3 cache for the 8-core multi-threaded Xeon® Processor

Jonathan Chang, Szu-Liang Chen, Siufu Chiu, 2009, 2009 Symposium on VLSI Circuits.

A 22nm 2.5MB slice on-die L3 cache for the next generation Xeon® processor

Wei Chen, Szu-Liang Chen, Siufu Chiu, 2013, 2013 Symposium on VLSI Technology.