Dae-Je Chin

Variable V CC Design Techniques for Battery-Operated DRAM's

Seung-Moon Yoo, Seung-Hoon Lee, Soo-In Cho, 1993 .

16 Mbit synchronous DRAM with 125 Mbyte/sec data rate

Tae-Jin Kim, Soo-In Cho, Seung-Hoon Lee, 1993, Symposium 1993 on VLSI Circuits.

A process for preparing a storage capacitor for a semiconductor memory cell

Young-Woo Park, Tae-Young Chung, Dae-Je Chin, 1992 .

Temperature-compensation circuit techniques for high-density CMOS DRAMs

Dong-Sun Min, Dae-Je Chin, Yong-Sik Seok, 1992 .

Variable V_<CC> Design Techniques for Battery-Operated DRAM's (Special Section on the 1992 VLSI Circuits Symposium)

Seung-Moon Yoo, Seung-Hoon Lee, Soo-In Cho, 1993 .

16-Mb synchronous DRAM with 125-Mbyte/s data rate

Tae-Jin Kim, Soo-In Cho, Seung-Hoon Lee, 1994 .

An experimental 16-Mbit DRAM with reduced peak-current noise

Soo-In Cho, Changhyun Kim, Dong-Sun Min, 1989 .