S. Miura

发表

Electrical Properties of YBa~2Cu~3O~x Films Grown by Liquid Phase Epitaxy

K. Suzuki, T. Morishita, S. Miura, 1998 .

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

Shoji Ikeda, Yitao Ma, Tetsuo Endoh, 2016 .

A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

T. Endoh, T. Ohsawa, S. Ikeda, 2013, 2013 Symposium on VLSI Circuits.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

Shoji Ikeda, Yitao Ma, Tetsuo Endoh, 2017 .

Real-time H.264 Encoder with Deblocking Filter Parallelization

S. Miura, T. Moriyoshi, 2008, 2008 Digest of Technical Papers - International Conference on Consumer Electronics.

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, 2015 .

A 16-Mb Toggle MRAM With Burst Modes

N. Kasai, N. Sakimura, K. Mori, 2007, IEEE Journal of Solid-State Circuits.

Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine

T. Endoh, S. Fukami, S. Ikeda, 2013, 2013 Symposium on VLSI Technology.

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, 2015 .

A Power-gated 32bit MPU with a Power Controller Circuit Activated by Deep-sleep-mode Instruction Achieving Ultra-low Power Operation

Tetsuo Endoh, Takahiro Hanyu, H. Ohno, 2014 .

Cleaved surfaces of high Tc films for making SNS structures

S. Miura, Yoshikatsu Kojima, Shinji Matsui, 1991, Other Conferences.

Design and process integration for high-density, high-speed, and low-power 6F/sup 2/ cross point MRAM cell

H. Aikawa, T. Kajiyama, S. Miura, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A content addressable memory using magnetic domain wall motion cells

T. Endoh, S. Fukami, N. Kasai, 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.

A 512kb cross-point cell MRAM

N. Sakimura, S. Miura, S. Tahara, 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop

T. Endoh, T. Ohsawa, H. Koike, 2013, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC).

MRAM-writing circuitry to compensate for thermal-variation of magnetization-reversal current

N. Sakimura, S. Miura, S. Tahara, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

Process Integration of Low-Power and High-Speed 16Mb MRAM using Multi-Layer Wiring Technology

S. Miura, Akihiro Nitayama, Hiroaki Yoda, 2006 .

Spintronics primitive gate with high error correction efficiency 6(Perror)2 for logic-in memory architecture

T. Endoh, S. Fukami, N. Kasai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

S. Fukami, S. Ikeda, N. Kasai, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Magnetic and Writing Properties of Clad Lines in a Toggle MRAM

S. Miura, S. Tahara, H. Hada, 2006, INTERMAG 2006 - IEEE International Magnetics Conference.

Toggling cell with four antiferromagnetically coupled ferromagnetic layers for high density MRAM with low switching current

S. Miura, S. Tahara, Y. Asao, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

First demonstration of field-free SOT-MRAM with 0.35 ns write speed and 70 thermal stability under 400°C thermal tolerance by canted SOT structure and its advanced patterning/SOT channel technology

T. Endoh, S. Fukami, S. Ikeda, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

Novel Quad interface MTJ technology and its first demonstration with high thermal stability and switching efficiency for STT-MRAM beyond 2Xnm

T. Endoh, S. Ikeda, S. Miura, 2019, 2019 Symposium on VLSI Technology.

Magnetic and Writing Properties of Clad Lines Used in a Toggle MRAM

S. Miura, S. Tahara, H. Hada, 2006, IEEE Transactions on Magnetics.

A 1.5nsec/2.1nsec random read/write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories

T. Ohsawa, T. Endoh, S. Ikeda, 2013, 2013 Symposium on VLSI Technology.

27.4 A 90nm 12ns 32Mb 2T1MTJ MRAM

Naoki Kasai, S. Miura, Hiroaki Honjo, 2009 .

A 16Mb toggle MRAM with burst modes

S. Fukami, N. Kasai, N. Sakimura, 2006, 2006 IEEE Asian Solid-State Circuits Conference.