Toshiyuki Takewaki

发表

CMOS device optimization for system-on-a-chip applications

Kiyotaka Imai, K. Yamaguchi, K. Matsui, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

Chip-Level Performance Improvement Using Triple Damascene Wiring Design Concept for the 0.13 µm CMOS Generation and Beyond

Kazuhiro Takeda, Masahiro Ikeda, Tomoaki Tanaka, 2006, IEICE Trans. Electron..

Accurate Modeling Method for Cu Interconnect

Norio Okada, Makoto Yasuda, Manabu Iguchi, 2008, IEICE Trans. Electron..

Characterizing Film Quality and Electromigration Resistance of Giant-Grain Copper Interconnects (Special Issue on Sub-Half Micron Si Device and Process Technologies)

Tadahiro Ohmi, Tadashi Shibata, Takahisa Nitta, 1993 .