M. Badaroglu

发表

Flexible OFDM transceiver for a high-speed wireless LAN

W. Eberle, M. Badaroglu, V. Derudder, 1999, Gateway to 21st Century Communications Village. VTC 1999-Fall. IEEE VTS 50th Vehicular Technology Conference (Cat. No.99CH36324).

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

P. Wambacq, M. Badaroglu, H.J. De Man, 2004, IEEE Journal of Solid-State Circuits.

Metrology for the next generation of semiconductor devices

M. Badaroglu, Y. Obeng, N. G. Orji, 2018, Nature Electronics.

Modeling of Substrate Noise Generation, Isolation, and Impact for an LC-VCO and a Digital Modem on a Lightly-Doped Substrate

P. Wambacq, M. Badaroglu, M. Kuijk, 2006, IEEE Journal of Solid-State Circuits.

Implementation of an efficient lattice digital ladder filter for up/down conversion in an OFDM-WLAN system

M. Badaroglu, S. Donnay, S. Signell, 2001, Proceedings of the 27th European Solid-State Circuits Conference.

BANDIT: embedding analog-to-digital converters on digital telecom ASICs

M. Badaroglu, I. Bolsens, M. Engels, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Modeling and experimental verification of substrate noise generation in a 220Kgates WLAN system–on–chip with multiple supplies

H. De Man, M. Badaroglu, S. Signell, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

UWB Search Strategies for Minimal-Length Preamble and a Low-Complexity Analog Receiver

C. Desset, J. Ryckaert, M. Badaroglu, 2006, 2006 IEEE 7th Workshop on Signal Processing Advances in Wireless Communications.

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

H. De Man, G. Van der Plas, M. Badaroglu, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

Publisher Correction: Metrology for the next generation of semiconductor devices

M. Badaroglu, Y. Obeng, N. G. Orji, 2018 .

Carrier-based UWB impulse radio: simplicity, flexibility, and pulser implementation in 0.18-micron CMOS

C. Desset, P. Wambacq, J. Ryckaert, 2005, 2005 IEEE International Conference on Ultra-Wideband.

Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification

H. De Man, M. Badaroglu, I. Bolsens, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits

H. De Man, M. Badaroglu, M. van Heijningen, 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

Fast simulation of power electronic systems by partitioning, segmentation and caching

M. Badaroglu, S. Nagai, N. Otsuka, 2012, 2012 IEEE 13th Workshop on Control and Modeling for Power Electronics (COMPEL).

A digital 80 Mb/s OFDM transceiver IC for wireless LAN in the 5 GHz band

M. Badaroglu, V. Derudder, S. Thoen, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

Extreme scaling enabled by 5 tracks cells: Holistic design-device co-optimization for FinFETs and lateral nanowires

J. Ryckaert, D. Verkest, M. Badaroglu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

M. Badaroglu, L. Witters, D. Mocuta, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

H. De Man, M. Badaroglu, G. Gielen, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

Modeling and experimental verification of substrate coupling and isolation techniques in mixed-signal ICs on a lightly-doped substrate

G. Van der Plas, M. Badaroglu, S. Donnay, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

A. Mercha, D. Verkest, M. Badaroglu, 2012, International Electron Devices Meeting.