Paul Wielage

发表

Design and DfT of a High-Speed Area-Efficient Embedded Asynchronous FIFO

Erik Jan Marinissen, Paul Wielage, Michel Altheimer, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis

Paul Wielage, Richard P. Kleihorst, Marc J. M. Heijligers, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Service-based design of systems on chip and networks on chip

Om Prakash Gangwal, Paul Wielage, John Dielissen, 2005 .

Networks on silicon: combining best-effort and guaranteed services

Kees G. W. Goossens, Ad M. G. Peeters, Paul Wielage, 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

Clock synchronization through handshake signalling

Ad M. G. Peeters, Paul Wielage, Suk-Jin Kim, 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration

Om Prakash Gangwal, Kees Goossens, Andrei Radulescu, 2005 .

Testing a pipeline in an integrated circuit

Paul Wielage, Kaam Kees Van, 2005 .

An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration

Kees G. W. Goossens, Om Prakash Gangwal, Andrei Radulescu, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Circuit with pseudo-multiport memory

Paul Wielage, P. Lodewijk Bellefroid, H. Leonardus Sevat, 1999 .

Networks on silicon: blessing or nightmare?

Kees G. W. Goossens, Paul Wielage, 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.

Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO

Erik Jan Marinissen, Erik Larsson, Paul Wielage, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration

Kees G. W. Goossens, Andrei Radulescu, Paul Wielage, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

Clock synchronization through handshake signalling

Paul Wielage, Suk-Jin Kim, Joep L. W. Kessels, 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

High-Quality Low-Cost Test and DfT for an Embedded Asynchronous FIFO

Erik G. Larsson, Erik Jan Marinissen, Paul Wielage, 2006 .

A process for the memory test

Erik Jan Marinissen, Paul Wielage, Guillaume E. A. Lousberg, 2000 .

A Router Architecture for Networks on Silicon

Kees Goossens, Paul Wielage, Edwin Rijpkema, 2001 .

5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filter

Paul Wielage, Daniël Schinkel, Lucien J. Breems, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Guaranteeing the Quality of Services in Networks on Chip

Kees G. W. Goossens, Andrei Radulescu, Paul Wielage, 2003, Networks on Chip.

HIFI: From Parallel Algorithm to Fixed-Size VLSI Processor Array

Ed F. Deprettere, Paul Wielage, Patrick Dewilde, 1993 .

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip

Kees G. W. Goossens, Andrei Radulescu, Paul Wielage, 2003, DATE.

MODEL AND METHODS FOR REGULAR ARRAY DESIGN

Ed F. Deprettere, Paul Wielage, Peter Held, 1993 .

A design system for massively parallel hardware

Ed F. Deprettere, Paul Wielage, Patrick Dewilde, 1994 .

Xetal: a low-power high-performance smart camera processor

Paul Wielage, Anteneh A. Abbo, Leo Sevat, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Clock Synchronization through Handshaking

Paul Wielage, Ad Peeters, Joep Kessels, .