Hiroaki Honjo

发表

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

Shoji Ikeda, Yitao Ma, Tetsuo Endoh, 2016 .

A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture

Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition

Yitao Ma, Takahiro Hanyu, Masaaki Niwa, 2020, IEEE Journal of Solid-State Circuits.

A spin transfer torque magnetoresistance random access memory-based high-density and ultralow-power associative memory for fully data-adaptive nearest neighbor search with current-mode similarity evaluation and time-domain minimum searching

Shoji Ikeda, Yitao Ma, Tetsuo Endoh, 2017 .

Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2013 .

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications

Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, 2013, IEICE Electron. Express.

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, 2015 .

A 90nm 12ns 32Mb 2T1MTJ MRAM

Yuichi Ito, Hiroaki Honjo, Yosuke Kobayashi, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

High-speed simulator including accurate MTJ models for spintronics integrated circuit design

Hiroki Koike, Tetsuo Endoh, Takahiro Hanyu, 2012, 2012 IEEE International Symposium on Circuits and Systems.

Demonstration of Yield Improvement for On-Via MTJ Using a 2-Mbit 1T-1MTJ STT-MRAM Test Chip

Shoji Ikeda, Hiroki Koike, Tetsuo Endoh, 2016, 2016 IEEE 8th International Memory Workshop (IMW).

12.1 An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

Power-gated 32 bit microprocessor with a power controller circuit activated by deep-sleep-mode instruction achieving ultra-low power operation

Shoji Ikeda, Tetsuo Endoh, Takahiro Hanyu, 2015 .

A Power-gated 32bit MPU with a Power Controller Circuit Activated by Deep-sleep-mode Instruction Achieving Ultra-low Power Operation

Tetsuo Endoh, Takahiro Hanyu, H. Ohno, 2014 .

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A 47.14- $\mu\text{W}$ 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications

Daisuke Suzuki, Shoji Ikeda, Hiroki Koike, 2019, IEEE Journal of Solid-State Circuits.

A 600-μW Ultra-Low-Power Associative Processor for Image Pattern Recognition Employing Magnetic Tunnel Junction (MTJ) Based Nonvolatile Memories with Novel Intelligent Power-Gating (IPG) Scheme

Yitao Ma, Tetsuo Endoh, Takahiro Hanyu, 2015 .

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

Shoji Ikeda, Hiroki Koike, Tetsuo Endoh, 2012, 2012 Symposium on VLSI Circuits (VLSIC).

A free-extendible and ultralow-power nonvolatile multi-core associative coprocessor based on MRAM with inter-core pipeline scheme for large-scale full-adaptive nearest pattern searching

Shoji Ikeda, Yitao Ma, Tetsuo Endoh, 2020, Japanese Journal of Applied Physics.

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2015, IEEE Journal of Solid-State Circuits.

1T1MTJ STT-MRAM Cell Array Design with an Adaptive Reference Voltage Generator for Improving Device Variation Tolerance

Shoji Ikeda, Hiroki Koike, Tetsuo Endoh, 2015, 2015 IEEE International Memory Workshop (IMW).

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Material Stack Design With High Tolerance to Process-Induced Damage in Domain Wall Motion Device

Hiroaki Honjo, Kunihiko Ishihara, Keizo Kinoshita, 2014, IEEE Transactions on Magnetics.

Design and fabrication of a perpendicular magnetic tunnel junction based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure.

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, Journal of applied physics.

A Recent Progress of Spintronics Devices for Integrated Circuit Applications

Tetsuo Endoh, Hiroaki Honjo, T. Endoh, 2018, Journal of Low Power Electronics and Applications.

Electrical endurance of Co/Ni wire for magnetic domain wall motion device

Shoji Ikeda, Hiroaki Honjo, Keizo Kinoshita, 2013 .

27.4 A 90nm 12ns 32Mb 2T1MTJ MRAM

Naoki Kasai, S. Miura, Hiroaki Honjo, 2009 .

Three-terminal magnetic tunneling junction device with perpendicular anisotropy CoFeB sensing layer

Hiroaki Honjo, Kunihiko Ishihara, Keizo Kinoshita, 2014 .

Co/Pt multilayer based reference layers in magnetic tunnel junctions for nonvolatile spintronics VLSIs

Shoji Ikeda, Hiroaki Honjo, Hideo Sato, 2014 .

Properties of perpendicular-anisotropy magnetic tunnel junctions fabricated over the bottom electrode contact

Shoji Ikeda, Tetsuo Endoh, Hiroaki Honjo, 2015 .

Magnetic tunneling junction with Fe/NiFeB free layer for magnetic logic circuits

Hiroaki Honjo, Hideo Ohno, Sadahiko Miura, 2012 .

Performance of shape-varying magnetic tunneling junction for high-speed magnetic random access memory cells

Hiroaki Honjo, Sadahiko Miura, Shunsuke Fukami, 2009 .

Critical Role of W Insertion Layer Sputtering Condition for Reference Layer on Magnetic and Transport Properties of Perpendicular-Anisotropy Magnetic Tunnel Junction

Shoji Ikeda, Tetsuo Endoh, Hiroaki Honjo, 2019, IEEE Transactions on Magnetics.

Damage Recovery by Reductive Chemistry after Methanol-Based Plasma Etch to Fabricate Magnetic Tunnel Junctions

Shoji Ikeda, Hiroaki Honjo, Keizo Kinoshita, 2012 .