K. Ueno

Floating Gate super multi level NAND Flash Memory Technology for 30nm and beyond

K. Uchida, S. Watanabe, S. Sato, 2008, 2008 IEEE International Electron Devices Meeting.

Development of KAGRA Algorithmic Library (KAGALI)

Kazuki Sakai, Kazuyuki Tanaka, Naoko Ohishi, 2017 .

Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS devices

S. Ohnishi, N. Kawahara, Y. Kakuhara, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

A Design Methodology Realizing an Over GHz Synthesizable Streaming Processing Unit

H. Murakami, Y. Urakawa, K. Ueno, 2007, 2007 IEEE Symposium on VLSI Circuits.