K. R. Nary

Dynamic latch for high speed GaAs domino circuits

S. I. Long, K. R. Nary, 1992 .

Two-phase dynamic FET logic: an extremely low power, high speed logic family for GaAs VLSI

S. I. Long, K. R. Nary, 1991, [1991] GaAs IC Symposium Technical Digest.

An 8-bit, 2 gigasample per second analog to digital converter

W. T. Colleran, K. C. Wang, S. Beccue, 1995, GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium 17th Annual Technical Digest 1995.

Ultralow-power GaAs MESFET MSI circuits using two-phase dynamic FET logic

Stephen I. Long, P. S. Lassen, K. R. Nary, 1993 .

GaAs two-phase dynamic FET logic: a low-power logic family for VLSI

S. I. Long, K. R. Nary, 1992 .

A 1 mW, 500 MHz 4-bit adder using two-phase dynamic FET logic gates

S. I. Long, K. R. Nary, 1992, GaAs IC Symposium Technical Digest 1992.

A model for coplanar waveguide transmission line structures on semiconductor substrates

S. I. Long, K. R. Nary, K. G. Bellare, 1993 .