T. Sakoda

A 100-Gbit/s 2:1 multiplexer in InP HEMT technology

T. Suzuki, Y. Nakasha, T. Takahashi, 2003, IEEE MTT-S International Microwave Symposium Digest, 2003.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

T. Miyashita, T. Sugii, S. Satoh, 2007, 2007 IEEE International Electron Devices Meeting.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

T. Miyashita, Y. Sambonsugi, T. Sugii, 2007, 2007 IEEE International Electron Devices Meeting.

Formation of HfSiON/SiO/sub 2//Si-substrate gate stack with low leakage current for high-performance high-/spl kappa/ MISFETs

M. Yamaguchi, T. Sakoda, H. Minakata, 2006, IEEE Transactions on Electron Devices.