Serge Biesemans

发表

Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFET's

Serge Biesemans, M. Hendriks, Stefan Kubicek, 1998 .

Comprehensive approach to MuGFET metrology

Rita Rooyackers, Philippe Leray, Shaunee Cheng, 2006, SPIE Advanced Lithography.

Analyzing block placement errors in SADP patterning

Carlos Fonseca, Satoru Shimura, Shinji Kobayashi, 2016, SPIE Advanced Lithography.

Advanced FinFET Devices for Sub-32nm Technology Nodes: Characteristics and Integration Challenges

Rita Rooyackers, Anabela Veloso, Liesbeth Witters, 2009 .

Pattern uniformity control in integrated structures

Carlos Fonseca, Satoru Shimura, Shinji Kobayashi, 2017, Advanced Lithography.

Nanoelectronics and More‐than‐Moore at IMEC

Wilfried Vandervorst, Serge Biesemans, Jo De Boeck, 2011 .

Multi-gate devices for the 32 nm technology node and beyond

Rita Rooyackers, Nadine Collaert, Isabelle Ferain, 2008 .

Image contrast enhancement of multiple patterning features through lower light source bandwidth

Serge Biesemans, Paolo Alagna, Greg Rechtsteiner, 2017, Advanced Lithography.

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Liesbeth Witters, Serge Biesemans, Stefan Kubicek, 2010 .

Simulation of Semiconductor Processes and Devices 1998: SISPAD 98

Serge Biesemans, Kristin De Meyer, Processes, 2012 .

Transport-based dopant mapping in advanced FinFETs

Gerhard Klimeck, Nadine Collaert, Serge Biesemans, 2008 .

Leff extraction for sub-100 nm MOSFET devices

Serge Biesemans, Qiuyi Ye, Q. Ye, 2004 .

A 4 K 2 K 60-fps Image Sensor Based on Stagger-laced Dual-exposure Technique

Jan Craninckx, Serge Biesemans, Bertrand Parvais, 2013 .

Simulation of Semiconductor Processes and Devices 1998

Serge Biesemans, Kristin De Meyer, 1998 .

High Hole Mobility in 65 nm Strained Ge p-Channel Field Effect Transistors with HfO2Gate Dielectric

Jerome Mitard, Jacopo Franco, Luigi Pantisano, 2011 .

Interface Trap Density Metrology from Sub-Threshold Transport in Highly Scaled Undoped Si n-FinFETs

Gerhard Klimeck, Serge Biesemans, Sven Rogge, 2011, 1102.0140.

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth

Rita Rooyackers, Nadine Collaert, Malgorzata Jurczak, 2008 .

NMOS and PMOS triple gate devices with mid-gap metal gate on oxynitride and Hf based gate dielectrics

Rita Rooyackers, Wim Deweerd, Tom Schram, 2005 .

Implant-Free SiGe Quantum Well pFET: A novel, highly scalable and low thermal budget device, featuring raised source/drain and high-mobility channel

Geert Hellings, Jerome Mitard, Liesbeth Witters, 2010, 2010 International Electron Devices Meeting.

Gate-induced quantum-confinement transition of a single dopant atom in a silicon FinFET

Insoo Woo, Gerhard Klimeck, Nadine Collaert, 2008 .

Migrating from planar to FinFET for further CMOS scaling: SOI or Bulk?

Rita Rooyackers, Liesbeth Witters, C. Ortolland, 2009, ESSDERC 2009.

PVD-HIGH-K GATE DIELECTRICS WITH FUSI GATE AND INFLUENCE OF PDA TREATMENT ON ON-STATE DRIVE CURRENT

Serge Biesemans, Shigenori Hayashi, S. Kubicek, 2006 .

Single-electron effects in heavily doped polycrystalline silicon nanowires

Serge Biesemans, Zahid A. K. Durrani, Haroon Ahmed, 1998 .