L. Hsu

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

G. Daniel, D. Hanson, M. Wordeman, 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture

G. Daniel, M. Wordeman, T. Kirihata, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

Mechanical design of a low concentration ratio solar array for a space station application

L. Hsu, M. S. Biss, 1983 .

A 200 MHz 2.5 V 4 W superscalar RISC microprocessor

H. Sanchez, C. Nicoletta, I. Vo, 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.