D. Netis

A 7F/sup 2/ cell and bitline architecture featuring tilted array devices and penalty-free vertical BL twists for 4 Gb DRAM's

G. Daniel, D. Hanson, M. Wordeman, 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).

A 390 mm/sup 2/ 16-bank 1 Gb DDR SDRAM with hybrid bitline architecture

G. Daniel, M. Wordeman, T. Kirihata, 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

A 113 mm/sup 2/ 600 Mb/s/pin 512 Mb DDR2 SDRAM with vertically-folded bitline architecture

M. Wordeman, T. Kirihata, D. Netis, 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).