Naveen John

A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor

Sung Kim, Xun Sun, Fahim ur Rahman, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Xun Sun, Fahim ur Rahman, Naveen John, 2019, IEEE Journal of Solid-State Circuits.

An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor

Keith A. Bowman, Sung Kim, Fahim ur Rahman, 2018, 2018 IEEE Symposium on VLSI Circuits.