Hye-Seung Yu

Comparative study in response time between a current-mode and a voltage-mode sense amplifier for resistive loads in MRAM

Soo-Won Kim, Sung-Jong Kim, Sang-Hun Song, 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).

An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin

Soo-Won Kim, Hye-Seung Yu, Jong-Chul Lim, 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Jae-Wook Lee, Reum Oh, Dong-Hak Shin, 2016, ISSCC.

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)

Yong-Hwan Kim, Jae-Hun Jung, Kyomin Sohn, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Reum Oh, Dong-Hak Shin, Jae-Hun Jung, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

An advanced bit-line clamping scheme in magnetic RAM for wide sensing margin

Soo-Won Kim, Hye-Seung Yu, Jong-Chul Lim, 2005, ASP-DAC.

Industry's First 7.2 Gbps 512GB DDR5 Module

Young-Soo Sohn, Tae-Young Oh, Gong-Heum Han, 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).